Design and allocation of loosely coupled multi-bit flip-flops for power reduction in post-placement optimization

Merging 1-bit flip-flops into multi-bit flip-flops in the post-placement stage is one of the most effective techniques for minimizing clock power. The obstacles that hinder the merging process for multi-bit flip-flops are (1) the input and output timing constraint on every flip-flop, (2) the area constraint on every partitioned bin in the placement plane, and (3) the routing capacity constraint on every bin edge. This work tries to eliminate constraint-1 and constraint-2 so that a full benefit of multi-bit flip-flops can be reaped. Precisely, rather than using the conventional structure of multi-bit flip-flops, we introduce a new style of multi-bit flip-flop, called loosely coupled multi-bit flip-flop (LC-MBFF). The merit of LC-MBFF is that the logically constituent 1-bit flip-flops in LC-MBFF can be physically apart (i.e., no relocation), providing no need to set aside white space in constraint-2 and no need to check timing in constraint-1. Utilizing LC-MBFFs, we propose a routability and clock-tree driven multi-bit flip-flop allocation algorithm, which fully explores the diverse allocation of LC-MBFF structures to maximally reduce clock power consumption. Experimental results with ISCAS89 and IWLS2005 benchmark circuits show that our proposed allocation algorithm using the newly designed multi-bit flip-flops is able to reduce on average the clock power by 8.50% while the best known multi-bit flip-flop allocation algorithm [7] reduces by 5.37%.

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