Network-on-Chip Implementation of Midimew-Connected Mesh Network

Architecture of interconnection network plays a significant role in the performance and energy consumption of Network-on-Chip (NoC) systems. In this paper we propose NoC implementation of Midi mew-connected Mesh Network (MMN). MMN is a Minimal Distance Mesh with Wrap-around (Midi mew) links network of multiple basic modules, in which the basic modules are 2D-mesh networks that are hierarchically interconnected for higher-level networks. For implementing all the links of level-3 MMN, minimum 4 layers are needed which is feasible with current and future VLSI technologies. With innovative combination of diagonal and hierarchical structure, MMN possesses several attractive features including constant node degree, small diameter, low cost, small average distance, and moderate bisection width than that of other conventional and hierarchical interconnection networks.

[1]  Eby G. Friedman,et al.  3-D Topologies for Networks-on-Chip , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[2]  Susumu Horiguchi,et al.  Dynamic communication performance of hierarchical interconnection network: H3D-Mesh , 2002 .

[3]  M. A. H. Akhand,et al.  A new hierarchical interconnection network for future generation parallel computer , 2014, 16th Int'l Conf. Computer and Information Technology.

[4]  M. Y. Simmons,et al.  A single atom transistor , 2012, 2012 IEEE Silicon Nanoelectronics Workshop (SNW).

[5]  Bin Cong,et al.  Scalable Parallel Computing: Technology, Architecture, Programming , 1999, Scalable Comput. Pract. Exp..

[6]  Axel Jantsch,et al.  A network on chip architecture and design methodology , 2002, Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002.

[7]  Behrooz Parhami,et al.  Perfect difference networks and related interconnection structures for parallel and distributed systems , 2005, IEEE Transactions on Parallel and Distributed Systems.

[8]  Axel Jantsch,et al.  Network on Chip : An architecture for billion transistor era , 2000 .

[9]  Luca Benini,et al.  Networks on Chips : A New SoC Paradigm , 2022 .

[10]  Yasushi Inoguchi,et al.  Symmetric and Folded Tori Connected Torus Network , 2011, J. Networks.

[11]  Partha Pratim Pande,et al.  Networks-on-Chip in a Three-Dimensional Environment: A Performance Evaluation , 2009, IEEE Transactions on Computers.

[12]  Jörg Henkel,et al.  On-chip networks: a scalable, communication-centric embedded system design paradigm , 2004, 17th International Conference on VLSI Design. Proceedings..

[13]  Susumu Horiguchi,et al.  Modified Hierarchical 3D-Torus Network , 2005, IEICE Trans. Inf. Syst..

[14]  Yang Yu,et al.  A RDT-based interconnection network for scalable network-on-chip designs , 2005, International Conference on Information Technology: Coding and Computing (ITCC'05) - Volume II.

[15]  Susumu Horiguchi,et al.  TTN: A High Performance Hierarchical Interconnection Network for Massively Parallel Computers , 2009, IEICE Trans. Inf. Syst..

[16]  Giovanni De Micheli Reliable communication in systems on chips , 2004, Proceedings. 41st Design Automation Conference, 2004..

[17]  M. M. Hafizur Rahman,et al.  Network-on-chip implementation of hierarchical torus network , 2013 .