Waveform Engineering at Gate Node of Class-J Power Amplifiers

In this paper, the class-J mode of operation is investigated when sinusoidal, half-sinusoidal (HS), triangle, pulse, and reduced conduction angle voltage waveforms are shaped at the gate node of the transistor. Output power, maximum power-added efficiency (PAE), large signal gain (LSG), and load–pull contours are presented and compared for each input signal. It is shown that PAE of a class-J power amplifier (PA) is improved when an HS voltage is realized at the gate node of the transistor. This enhancement can also be observed for a pulse input with 20% duty cycle, however, at the expense of reduced output power and LSG. A proof-of-concept, two-stage class-J PA is designed and fabricated in a 0.25-<inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> AlGaAs-InGaAs pHEMT technology. The prototype PA is based on an HS gate voltage for the second-stage transistor, which operates in class-J mode. The driver stage also works in class-J mode to provide an HS voltage at its drain node, and the interstage matching network is designed to convey this waveform to gate of the second-stage transistor. Chip dimensions are <inline-formula> <tex-math notation="LaTeX">$1.99\times1.24$ </tex-math></inline-formula> mm², and 26.6–27.2-dBm output power with ≥50% PAE is achieved over the 0.92–1.4-GHz bandwidth.