A combined interval and floating point multiplier

Interval arithmetic provides an efficient method for monitoring and controlling errors in numerical calculations. However, existing software packages for interval arithmetic are often too slow for numerically intensive computations. This paper presents the design of a multiplier that performs either interval or floating point multiplication. This multiplier requires only slightly more area and delay than a conventional floating point multiplier, and is one to two orders of magnitude faster than software implementations of interval multiplication.

[1]  Michael J. Schulte Hardware interval multipliers , 1996, RITA.

[2]  Christoph Baumhof A new VLSI vector arithmetic coprocessor for the PC , 1995, Proceedings of the 12th Symposium on Computer Arithmetic.

[3]  Earl E. Swartzlander,et al.  Reduced area multipliers , 1993, Proceedings of International Conference on Application Specific Array Processors (ASAP '93).

[4]  Mark Horowitz,et al.  Rounding algorithms for IEEE multipliers , 1989, Proceedings of 9th Symposium on Computer Arithmetic.

[5]  M. Slater The future of microprocessors , 1996 .

[6]  A. Knöfel A Hardware Kernel for Scientific/Engineering Computations , 1993 .

[7]  Earl E. Swartzlander,et al.  Parallel reduced area multipliers , 1995, J. VLSI Signal Process..

[8]  G. W. Walster The Extended Real Interval System , 1998 .

[9]  Christian P. Ullrich,et al.  Computer Arithmetic and Self-Validating Numerical Methods , 1990, Notes and reports in mathematics in science and engineering.

[10]  George F. Corliss Industrial Applications of Interval Techniques , 1990, Computer Arithmetic and Self-Validating Numerical Methods.

[11]  Earl E. Swartzlander,et al.  Variable-precision, interval arithmetic coprocessors , 1996, Reliab. Comput..

[12]  R. Baker Kearfott,et al.  Algorithm 681: INTBIS, a portable interval Newton/bisection package , 1990, TOMS.