Accurate Assessment of Bundled-Data Asynchronous NoCs Enabled by a Predictable and Efficient Hierarchical Synthesis Flow

Asynchronous interconnect technology leveraging transition signaling bundled-data is gaining momentum as a promising solution for the chip-level connectivity of GALS (Globally Asynchronous Locally Synchronous) integrated systems. However, the scope of most previous bundled-data network-on-chip (NoC) validations is limited to NoC switches in isolation. Studies with a broader scope admittedly end up in unstable results because of the incompleteness or low-maturity of the synthesis flow for asynchronous NoCs. By investing in the development of a predictable and hierarchical composition tool flow of NoC switches, this paper aims at major depth and insight in the comparative assessment of a complete bundled-data NoC with a competitive synchronous counterpart, when targeting an ultra-low power technology library.

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