On Evolutionary Synthesis of Compact Polymorphic Combinational Circuits

Polymorphic gates are unconventional circuit components t hat are not supported by existing synthesis tools. This article presents new methods for synthesis of polymorphic circuits. Propose d methods, based on polymorphic binary decision diagrams and polymorphic multiplexing, extend the ordinary circuit repsentations with the aim of including polymorphic gates. In orde r to reduce the number of gates in circuits synthesized using p roposed methods, an evolutionary optimization based on Carte si n Genetic Programming (CGP) is implemented. The implementations of polymorphic circuits optimized by CGP represent the best known solutions if the number of gates is considered as t he decision criterion.

[1]  Lukás Fujcik,et al.  REPOMO32 - New reconfigurable polymorphic integrated circuit for adaptive hardware , 2009, 2009 IEEE Workshop on Evolvable and Adaptive Hardware.

[2]  Jordi Madrenas,et al.  Evolvable Systems: From Biology to Hardware , 1996, Lecture Notes in Computer Science.

[3]  Donald E. Knuth,et al.  The Art of Computer Programming: Volume 3: Sorting and Searching , 1998 .

[4]  Nawwaf N. Kharma,et al.  Evolving novel image features using Genetic Programming-based image transforms , 2009, 2009 IEEE Congress on Evolutionary Computation.

[5]  Julian Francis Miller,et al.  Evolution and Acquisition of Modules in Cartesian Genetic Programming , 2004, EuroGP.

[6]  Adrian Stoica,et al.  Three-Function Logic Gate Controlled by Analog Voltage , 2006 .

[7]  Lukás Sekanina,et al.  Polymorphic FIR Filters with Backup Mode Enabling Power Savings , 2009, 2009 NASA/ESA Conference on Adaptive Hardware and Systems.

[8]  Lukás Sekanina,et al.  Physical Demonstration of Polymorphic Self-Checking Circuits , 2008, 2008 14th IEEE International On-Line Testing Symposium.

[9]  Wenjian Luo,et al.  Designing polymorphic circuits with polymorphic gates: a general design approach , 2007, IET Circuits Devices Syst..

[10]  Wenjian Luo,et al.  Designing Polymorphic Circuits with Evolutionary Algorithm Based on Weighted Sum Method , 2007, ICES.

[11]  Rolf Drechsler,et al.  Binary Decision Diagrams - Theory and Implementation , 1998 .

[12]  Lukás Sekanina,et al.  Evolutionary Design of Gate-Level Polymorphic Digital Circuits , 2005, EvoWorkshops.

[13]  Masahiro Fujita,et al.  Multi-Terminal Binary Decision Diagrams: An Efficient Data Structure for Matrix Representation , 1997, Formal Methods Syst. Des..

[14]  Julian Francis Miller,et al.  The Automatic Acquisition, Evolution and Reuse of Modules in Cartesian Genetic Programming , 2008, IEEE Transactions on Evolutionary Computation.

[15]  Julian Francis Miller,et al.  Redundancy and computational efficiency in Cartesian genetic programming , 2006, IEEE Transactions on Evolutionary Computation.

[16]  Tatiana Kalganova,et al.  Evolving more efficient digital circuits by allowing circuit layout evolution and multi-objective fitness , 1999, Proceedings of the First NASA/DoD Workshop on Evolvable Hardware.

[17]  Robert K. Brayton,et al.  Logic Minimization Algorithms for VLSI Synthesis , 1984, The Kluwer International Series in Engineering and Computer Science.

[18]  Tsutomu Sasao,et al.  Logic Synthesis and Verification , 2013 .

[19]  Donald E. Knuth,et al.  The art of computer programming: sorting and searching (volume 3) , 1973 .

[20]  J. Miller,et al.  Cartesian Genetic Programming 1 , 2000 .

[21]  Adrian Stoica,et al.  Polymorphic Electronics , 2001, ICES.

[22]  Julian Francis Miller,et al.  Cartesian genetic programming , 2000, GECCO '10.

[23]  Julian Francis Miller,et al.  Self-modifying cartesian genetic programming , 2007, GECCO '07.

[24]  Zdenek Kotásek,et al.  Reduction of Test Vectors Volume by Means of Gate-Level Reconfiguration , 2008, 2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems.

[25]  Lukás Sekanina,et al.  Reducing the number of transistors in digital circuits using gate-level evolutionary design , 2007, GECCO '07.

[26]  Julian Francis Miller,et al.  Scalability problems of digital circuit evolution evolvability and efficient designs , 2000, Proceedings. The Second NASA/DoD Workshop on Evolvable Hardware.

[27]  R. Brooks The relationship between matter and life , 2001, Nature.

[28]  Julian Francis Miller,et al.  Principles in the Evolutionary Design of Digital Circuits—Part II , 2000, Genetic Programming and Evolvable Machines.

[29]  Lukás Sekanina,et al.  An Efficient Selection Strategy for Digital Circuit Evolution , 2010, ICES.

[30]  Gul Muhammad Khan,et al.  Evolution of cartesian genetic programs capable of learning , 2009, GECCO '09.

[31]  Lukás Sekanina,et al.  Image Filter Design with Evolvable Hardware , 2002, EvoWorkshops.

[32]  Adrian Stoica,et al.  On Polymorphic Circuits and Their Design Using Evolutionary Algorithms , 2002 .

[33]  Zdenek Kotásek,et al.  Polymorphic Gates in Design and Test of Digital Circuits , 2008, Int. J. Unconv. Comput..

[34]  Xin Guo,et al.  Taking evolutionary circuit design from experimentation to implementation: some useful techniques and a silicon demonstration , 2004 .

[35]  Lukás Sekanina,et al.  Gate-level optimization of polymorphic circuits using Cartesian Genetic Programming , 2009, 2009 IEEE Congress on Evolutionary Computation.

[36]  Richard Ruzicka On bifunctional polymorphic gates controlled by a special signal , 2008 .