Power Aware BDD-based Logic Synthesis Using Adiabatic Multiplexers

Binary decision diagrams (BDDs) play an important role in the synthesis, verification, and testing of VLSI circuits. In this paper, we have proposed a new BDD-based approach for the synthesis of dual-rail adiabatic MUX circuits. The method yields around 22% reduction in the number of MUX blocks for several benchmark circuits compared to the conventional approach. Simulation result using SPICE on 180 nm technology shows, on an average, 50% reduction in power consumption for frequency ranging up to 300 MHz compared to implementation with static CMOS MUX circuits. At 600 MHz, power saving is observed to be nearly 35%. It is envisaged that the proposed approach is useful in realizing low-power circuits

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