ATPG aspects of FSM verification

Algorithms are presented for finite state machine (FSM) verification and image computation which improve on the results of O. Coudert et al (1989), giving 1-4 orders of magnitude speedup. Novel features include primary input splitting-this PODEM feature enlarges the search space but shortens the search due to implications. Another new feature, identical subtree recombination, is shown to be effective for iterative networks (eg, serial multipliers). The free-variable recognition feature prevents unbalanced bipartitioning trees in tautological subspaces. Finally, reached set pruning is significant when the image contains large numbers of previously reached states.<<ETX>>

[1]  Alberto L. Sangiovanni-Vincentelli,et al.  Test generation for sequential circuits , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[2]  Carl Pixley Introduction to a Computational Theory and Implementation of Sequential Hardware Equivalence , 1990, CAV.

[3]  Srinivas Devadas,et al.  Test generation for highly sequential circuits , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[4]  Olivier Coudert,et al.  Formal Boolean manipulations for the verification of sequential machines , 1990, Proceedings of the European Design Automation Conference, 1990., EDAC..

[5]  Srinivas Devadas,et al.  On the verification of sequential machines at differing levels of abstraction , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[6]  Prabhakar Goel,et al.  An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits , 1981, IEEE Transactions on Computers.

[7]  P. N. Loewenstein Formal verification of state-machines using higher-order logic , 1989, Proceedings 1989 IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[8]  Randal E. Bryant,et al.  Efficient implementation of a BDD package , 1991, DAC '90.

[9]  David Bryan,et al.  Combinational profiles of sequential benchmark circuits , 1989, IEEE International Symposium on Circuits and Systems,.