ATPG aspects of FSM verification
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Seh-Woong Jeong | Eric M. Schwarz | Fabio Somenzi | Gary D. Hachtel | Bernard Plessier | Hyunwoo Cho
[1] Alberto L. Sangiovanni-Vincentelli,et al. Test generation for sequential circuits , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[2] Carl Pixley. Introduction to a Computational Theory and Implementation of Sequential Hardware Equivalence , 1990, CAV.
[3] Srinivas Devadas,et al. Test generation for highly sequential circuits , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.
[4] Olivier Coudert,et al. Formal Boolean manipulations for the verification of sequential machines , 1990, Proceedings of the European Design Automation Conference, 1990., EDAC..
[5] Srinivas Devadas,et al. On the verification of sequential machines at differing levels of abstraction , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[6] Prabhakar Goel,et al. An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits , 1981, IEEE Transactions on Computers.
[7] P. N. Loewenstein. Formal verification of state-machines using higher-order logic , 1989, Proceedings 1989 IEEE International Conference on Computer Design: VLSI in Computers and Processors.
[8] Randal E. Bryant,et al. Efficient implementation of a BDD package , 1991, DAC '90.
[9] David Bryan,et al. Combinational profiles of sequential benchmark circuits , 1989, IEEE International Symposium on Circuits and Systems,.