Implementation of pipelined LMS adaptive filter for low-power VLSI applications

In this paper, we described the implementation of a pipelined low-power 6 taps adaptive filter, based on the least-mean square (LMS) algorithm. The process of the power characterization procedure is very efficient and can be easily set in synthesis based design flows without too much additional effort. The architecture shows a novel tradeoff between algorithmic performance and power dissipation. In this work, we also characterized the power with a natural top-down design methodology with iterative improvement.