A new prediction model for effects of plasma-induced damage on parameter variations in advanced LSIs

This paper proposes a physics-based variability prediction model integrating the effects of plasma-induced damage (PID) in advanced LSIs. We focus on charging damage to high-k gate dielectrics and physical damage (Si recess by ion bombardment). In addition to gate length-variation which has been discussed so far as a dominant factor for (static) variability, we demonstrate how PID impacts on – increases – the parameter variation (e.g., σVth), by employing both experimental PID data for high-k and Si substrate damage and a Monte Carlo method. The model prediction suggests a considerable increase in parameter variations by PID such as threshold voltage and off-state leakage.

[1]  S. Satoh,et al.  Effects of Gate Line Width Roughness on Threshold-Voltage Fluctuation Among Short-Channel Transistors at High Drain Voltage , 2010, IEEE Electron Device Letters.

[2]  E. Beigne,et al.  Statistical leakage modeling in CMOS logic gates considering process variations , 2008, 2008 IEEE International Conference on Integrated Circuit Design and Technology and Tutorial.

[3]  Koji Eriguchi,et al.  Quantitative and comparative characterizations of plasma process-induced damage in advanced metal-oxide-semiconductor devices , 2008 .

[4]  Wojciech Maly,et al.  Detection of an antenna effect in VLSI designs , 1996, Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

[5]  K. Eriguchi,et al.  A new framework for performance prediction of advanced MOSFETs with plasma-induced recess structure and latent defect site , 2008, 2008 IEEE International Electron Devices Meeting.

[6]  K. Eriguchi,et al.  Plasma-Induced Defect-Site Generation in Si Substrate and Its Impact on Performance Degradation in Scaled MOSFETs , 2009, IEEE Electron Device Letters.

[7]  Keith A. Bowman,et al.  Impact of Die-to-Die and Within-Die Parameter Variations on the Clock Frequency and Throughput of Multi-Core Processors , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[8]  Koji Eriguchi,et al.  Comprehensive Modeling of Threshold Voltage Variability Induced by Plasma Damage in Advanced Metal-Oxide-Semiconductor Field-Effect Transistors , 2010 .

[9]  Athanasios Papoulis,et al.  Probability, Random Variables and Stochastic Processes , 1965 .

[10]  Dirk Stroobandt,et al.  The interpretation and application of Rent's rule , 2000, IEEE Trans. Very Large Scale Integr. Syst..

[11]  K. Eriguchi,et al.  Effects of Plasma-Induced Si Recess Structure on n-MOSFET Performance Degradation , 2009, IEEE Electron Device Letters.

[12]  G. Kadamati,et al.  Automated antenna detection and correction methodology in VLSI designs , 2003, 2003 8th International Symposium Plasma- and Process-Induced Damage..

[13]  Modeling the effects of plasma-induced physical damage on subthreshold leakage current in scaled MOSFETs , 2010, 2010 IEEE International Conference on Integrated Circuit Design and Technology.

[14]  C. Gabriel,et al.  Quantifying a simple antenna design rule , 2000, 2000 5th International Symposium on Plasma Process-Induced Damage (IEEE Cat. No.00TH8479).

[15]  Koji Eriguchi,et al.  Model for Bias Frequency Effects on Plasma-Damaged Layer Formation in Si Substrates , 2010 .

[16]  Bruno O. Shubert,et al.  Random variables and stochastic processes , 1979 .

[17]  Borivoje Nikolic,et al.  Measurement and Analysis of Variability in 45 nm Strained-Si CMOS Technology , 2009, IEEE Journal of Solid-State Circuits.

[18]  Kin P. Cheung,et al.  Plasma Charging Damage , 2000 .