High Performance Level-Converting Flip-Flop with a Simple Pulse Generator and a Fast Latch

This paper proposes a high-performance levelconverting flip-flop (LCFF) for multi-V DD systems, called the explicit pulse-triggered dual-pass-transistor flip-flop (EPDFF). The proposed EPDFF provides both low power and high speed operations through the use of a simple pulse generator and a simple latch with a short signal propagation path. In experiments, EPDFF outperformed six existing LCFFs in both power consumption and delay in its operating range. After optimization for the minimum power-delay product (PDP), EPDFF had 19.4~52.6% less PDP than existing LCFFs, and had the smallest transistor area among the seven LCFFs we compared.

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