A retargetable framework for compiler/architecture co-development

Compiler-in-the-Loop (CiL) architecture exploration is widely accepted as being the right track for fast development of Application Specific Instruction-set Processors (ASIP). In this context, both, automatic application-specific Instruction Set Extension (ISE) and code generation by a compiler have received huge attention in the past. Together, both techniques enable processor designers to quickly adapt a processor’s Instruction Set Architecture (ISA) to the needs of a certain set of applications and to provide an appropriate high-level programming model. This manuscript presents a tool flow for identification and utilization of Custom Instructions (CIs) during architecture exploration in an automated fashion. By embedding this tool flow in an industry-proven architecture exploration framework, a methodology for simultaneous compiler/architecture co-exploration is derived. The advantage of the presented tool flow lies in its ability to develop a reusable ISA and an appropriate compiler for a set of applications and therefore to support the design of programmable architectures. In addition, ASIP architecture exploration is effectively improved since time consuming application analysis and compiler retargeting is automated. Through compilation and simulation of several benchmarks in accordance to extended ISAs, reliable feedback on speedup, code size and usability of identified CIs is provided. Furthermore, results on area consumption for extended ISAs are presented in order to compare the obtained speedup with the invested hardware effort of new CIs.

[1]  Scott A. Mahlke,et al.  IMPACT: an architectural framework for multiple-instruction-issue processors , 1991, ISCA '91.

[2]  Paolo Ienne,et al.  Automatic topology-based identification of instruction-set extensions for embedded processors , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

[3]  Rajiv Gupta.  Generalized dominators and post-dominators , 1992, POPL '92.

[4]  David Ryan Koes,et al.  Near-optimal instruction selection on dags , 2008, CGO '08.

[5]  Rainer Leupers,et al.  Architecture exploration for embedded processors with LISA , 2002 .

[6]  Aviral Shrivastava,et al.  A customizable compiler framework for embedded systems , 2001 .

[7]  Paolo Bonzini,et al.  A Retargetable Framework for Automated Discovery of Custom Instructions , 2007, 2007 IEEE International Conf. on Application-specific Systems, Architectures and Processors (ASAP).

[8]  Koen Bertels,et al.  The Instruction-Set Extension Problem: A Survey , 2008, TRETS.

[9]  Nikil D. Dutt,et al.  Functional abstraction driven design space exploration of heterogeneous programmable architectures , 2001, International Symposium on System Synthesis (IEEE Cat. No.01EX526).

[10]  Koichi Yamazaki,et al.  A note on greedy algorithms for the maximum weighted independent set problem , 2003, Discret. Appl. Math..

[11]  Kingshuk Karuri,et al.  A design flow for configurable embedded processors based on optimized instruction set extension synthesis , 2006, Proceedings of the Design Automation & Test in Europe Conference.

[12]  Jason Cong,et al.  Application-specific instruction generation for configurable processor architectures , 2004, FPGA '04.

[13]  Rainer Leupers,et al.  A universal technique for fast and flexible instruction-set architecture simulation , 2002, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[14]  Paolo Ienne,et al.  Rethinking custom ISE identification: a new processor-agnostic method , 2007, CASES '07.

[15]  Kingshuk Karuri,et al.  A methodology and tool suite for C compiler generation from ADL processor models , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[16]  Paolo Bonzini,et al.  Polynomial-time subgraph enumeration for automated instruction set extension , 2007 .

[17]  Alois Knoll,et al.  Automated generation of DSP program development tools using a machine description formalism , 1993, 1993 IEEE International Conference on Acoustics, Speech, and Signal Processing.

[18]  Bernhard Scholz,et al.  Register allocation for irregular architectures , 2002, LCTES/SCOPES '02.

[19]  Yoshinori Takeuchi,et al.  Synthesizable HDL Generation for Pipelined Processors from a Micro-Operation Description (Special Section of Selected Papers from the 12th Workshop on Circuit and Systems in Karuizawa) , 2000 .

[20]  T. C. May,et al.  Instruction-set matching and selection for DSP and ASIP code generation , 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.

[21]  Scott Mahlke,et al.  Processor acceleration through automated instruction set customization , 2003, Proceedings. 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003. MICRO-36..

[22]  David S. Johnson,et al.  Computers and Intractability: A Guide to the Theory of NP-Completeness , 1978 .

[23]  Paolo Ienne,et al.  Fast, quasi-optimal, and pipelined instruction-set extensions , 2008, 2008 Asia and South Pacific Design Automation Conference.

[24]  Gert Goossens,et al.  Chess: retargetable code generation for embedded DSP processors , 1994, Code Generation for Embedded Processors.

[25]  Rainer Leupers,et al.  Optimized ASIP synthesis from architecture description language models , 2007 .

[26]  Kurt Keutzer,et al.  Building ASIPs: The Mescal Methodology , 2006 .

[27]  Rainer Leupers,et al.  A code-generator generator for Multi-Output Instructions , 2007, 2007 5th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

[28]  Mario Vento,et al.  A (sub)graph isomorphism algorithm for matching large graphs , 2004, IEEE Transactions on Pattern Analysis and Machine Intelligence.

[29]  Scott A. Mahlke,et al.  Scalable subgraph mapping for acyclic computation accelerators , 2006, CASES '06.

[30]  Andreas Fauth.  Beyond tool-specific machine descriptions , 1994, Code Generation for Embedded Processors.

[31]  Nikil D. Dutt,et al.  EXPRESSION: a language for architecture exploration through compiler/simulator retargetability , 1999, Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078).

[32]  Paolo Ienne,et al.  Exact and approximate algorithms for the extension of embedded processor instruction sets , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[33]  Nikil D. Dutt,et al.  Automatic Identification of Application-Specific Functional Units with Architecturally Visible Storage , 2006, Proceedings of the Design Automation & Test in Europe Conference.

[34]  Heinrich Meyr,et al.  A novel methodology for the design of application-specificinstruction-set processors (ASIPs) using a machine description language , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[35]  Bernhard Scholz,et al.  Code Instruction Selection Based on SSA-Graphs , 2003, SCOPES.

[36]  B. Ramakrishna Rau,et al.  Elcor's Machine Description System: Version 3.0 , 1998 .

[37]  M. Anton Ertl.  Optimal code selection in DAGs , 1999, POPL '99.

[38]  Rainer Leupers,et al.  Instruction selection for embedded DSPs with complex instructions , 1996, Proceedings EURO-DAC '96. European Design Automation Conference with EURO-VHDL '96 and Exhibition.

[39]  Paolo Bonzini,et al.  Recurrence-Aware Instruction Set Selection for Extensible Embedded Processors , 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[40]  Marc Moonen,et al.  Signal Processing VI: Theories and Applications , 2012 .

[41]  Tulika Mitra,et al.  Disjoint Pattern Enumeration for Custom Instructions Identification , 2007, 2007 International Conference on Field Programmable Logic and Applications.

[42]  Günhan Dündar,et al.  An integer linear programming approach for identifying instruction-set extensions , 2005, 2005 Third IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'05).

[43]  Sharad Malik,et al.  Using register-transfer paths in code generation for heterogeneous memory-register architectures , 1996, DAC '96.

[44]  Robert K. Brayton,et al.  HW/SW partitioning and code generation of embedded control applications on a reconfigurable architecture platform , 2002, Proceedings of the Tenth International Symposium on Hardware/Software Codesign. CODES 2002 (IEEE Cat. No.02TH8627).

[45]  Douglas L. Maskell,et al.  Fast Identification of Custom Instructions for Extensible Processors , 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[46]  Alois Knoll,et al.  Implementation of complex DSP systems using High-Level Design Tools , 1994 .

[47]  Henk Corporaal,et al.  Designing domain-specific processors , 2001, CODES '01.

[48]  Gert Goossens,et al.  Code Generation for Embedded Processors , 1995 .

[49]  Bernhard Scholz,et al.  Addressing mode selection , 2003, International Symposium on Code Generation and Optimization, 2003. CGO 2003..

[50]  Stamatis Vassiliadis,et al.  Automatic selection of application-specific instruction-set extensions , 2006, Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06).

[51]  Christopher W. Fraser,et al.  Engineering E cient Code Generators using Tree Matching and Dynamic Programming , 2007 .

[52]  Tulika Mitra,et al.  Scalable custom instructions identification for instruction-set extensible processors , 2004, CASES '04.

[53]  Julian R. Ullmann,et al.  An Algorithm for Subgraph Isomorphism , 1976, J. ACM.

[54]  Nils J. Nilsson,et al.  Principles of Artificial Intelligence , 1980, IEEE Transactions on Pattern Analysis and Machine Intelligence.

[55]  Kurt Keutzer,et al.  Instruction selection using binate covering for code size optimization , 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[56]  Jürgen Teich,et al.  A joined architecture/compiler design environment for ASIPs , 2000, CASES '00.

[57]  Paolo Bonzini,et al.  Code transformation strategies for extensible embedded processors , 2006, CASES '06.

[58]  Giovanni De Micheli,et al.  Automatic instruction set extension and utilization for embedded processors , 2003, Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors. ASAP 2003.

[59]  Ricardo E. Gonzalez,et al.  Xtensa: A Configurable and Extensible Processor , 2000, IEEE Micro.

[60]  Kurt Keutzer,et al.  Network Processors: Origin of Species , 2002 .

[61]  J.D. Day,et al.  The OSI reference model , 1983 .

[62]  Majid Sarrafzadeh,et al.  Instruction generation and regularity extraction for reconfigurable processors , 2002, CASES '02.

[63]  Alfred V. Aho,et al.  Code generation using tree matching and dynamic programming , 1989, ACM Trans. Program. Lang. Syst..

[64]  Scott A. Mahlke,et al.  Automated custom instruction generation for domain-specific processor acceleration , 2005, IEEE Transactions on Computers.

[65]  Darin Petkov,et al.  Automatic generation of application specific processors , 2003, CASES '03.