A semi-formal min-cost buffer insertion technique considering multi-mode multi-corner timing constraints

Buffer Insertion has always been the most effective approach for timing optimization in VLSI designs. However, the emerging low-power design paradigm and the consideration of multiple operation modes and process corners (MMMC) have raised great challenges. Traditional dynamic-programming-based techniques are unable to cope with these challenges. In this paper, we develop a novel buffer insertion algorithm that utilizes a neighborhood restriction to simplify the constraint formulation and apply a semi-formal buffer refinement process to minimize buffer cost. The experimental results show that our tool can significantly reduce the buffer cost while meeting the MMMC timing constraints.

[1]  Jinjun Xiong,et al.  Buffer insertion considering process variation , 2005, Design, Automation and Test in Europe.

[2]  Jiang Hu,et al.  Path-Based Buffer Insertion , 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[3]  Rudy Lauwereins,et al.  Design, Automation, and Test in Europe , 2008 .

[4]  Weiping Shi,et al.  An O(nlogn) time algorithm for optimal buffer insertion , 2003, DAC '03.

[5]  Hai Zhou,et al.  Fast Min-Cost Buffer Insertion under Process Variations , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[6]  Weiping Shi,et al.  Complexity analysis and speedup techniques for optimal buffer insertion with minimum cost , 2004 .

[7]  Hai Zhou,et al.  An efficient buffer insertion algorithm for large networks based on Lagrangian relaxation , 1999, Proceedings 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.99CB37040).

[8]  Weiping Shi,et al.  Buffer insertion in large circuits with constructive solution search techniques , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[9]  Weiping Shi,et al.  Circuit-wise buffer insertion and gate sizing algorithm with scalability , 2008, 2008 45th ACM/IEEE Design Automation Conference.

[10]  Niklas Sörensson,et al.  Translating Pseudo-Boolean Constraints into SAT , 2006, J. Satisf. Boolean Model. Comput..

[11]  Liang Deng,et al.  Buffer insertion under process variations for delay minimization , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

[12]  L.P.P.P. van Ginneken,et al.  Buffer placement in distributed RC-tree networks for minimal Elmore delay , 1990 .

[13]  Salim Chowdhury,et al.  Repeater insertion for concurrent setup and hold time violations with power-delay trade-off , 2007, ISPD '07.

[14]  Weiping Shi,et al.  Complexity analysis and speedup techniques for optimal buffer insertion with minimum cost , 2004, ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).

[15]  Morteza Saheb Zamani,et al.  An Efficient Analytical Approach to Path-Based Buffer Insertion , 2007, IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07).