Technology-aware design of SRAM memory circuits

[1]  Athanasios Papoulis,et al.  Probability, Random Variables and Stochastic Processes , 1965 .

[2]  C. Sah,et al.  Effects of diffusion current on characteristics of metal-oxide (insulator)-semiconductor transistors☆ , 1966 .

[3]  R. E. Thomas,et al.  Carrier mobilities in silicon empirically related to doping and field , 1967 .

[4]  Nils J. Nilsson,et al.  Problem-solving methods in artificial intelligence , 1971, McGraw-Hill computer science series.

[5]  J. Meyer MOS models and circuit simulations , 1971 .

[6]  G. Declerck,et al.  Theory of the MOS transistor in weak inversion-new method to determine the number of surface states , 1975 .

[7]  G. Hachtel The simplicial approximation approach to design centering , 1977 .

[8]  E. Seevinck,et al.  Application of the translinear principle in digital circuits , 1978, IEEE Journal of Solid-State Circuits.

[9]  J. Bandler,et al.  Optimal centering, tolerancing, and yield determination via updated approximations and cuts , 1978 .

[10]  K. S. Tahim,et al.  A radial exploration approach to manufacturing yield estimation and design centering , 1979 .

[11]  J. Lohstroh Static and dynamic noise margins of logic circuits , 1979 .

[12]  R. Brayton,et al.  Yield maximization and worst-case design with arbitrary statistical distributions , 1980 .

[13]  J.D. Plummer,et al.  Electron mobility in inversion and accumulation layers on thermally oxidized silicon surfaces , 1980, IEEE Transactions on Electron Devices.

[14]  K. Singhal,et al.  Statistical design centering and tolerancing using parametric sampling , 1981 .

[15]  K. Antreich,et al.  Design centering by yield prediction , 1982 .

[16]  Stephen W. Director,et al.  A Design Centering Algorithm for Nonconvex Regions of Acceptability , 1982, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[17]  J. Lohstroh,et al.  Worst-case static noise margin criteria for logic circuits and their mathematical equivalence , 1983, IEEE Journal of Solid-State Circuits.

[18]  S. Russek,et al.  Semi-empirical equations for electron velocity in silicon: Part II—MOS inversion layer , 1983, IEEE Transactions on Electron Devices.

[19]  S.A. Schwarz,et al.  Semi-empirical equations for electron velocity in silicon: Part I—Bulk , 1983, IEEE Transactions on Electron Devices.

[20]  Judea Pearl,et al.  Heuristics : intelligent search strategies for computer problem solving , 1984 .

[21]  Y. Tsividis Operation and modeling of the MOS transistor , 1987 .

[22]  E. Seevinck,et al.  Static-noise margin analysis of MOS SRAM cells , 1987 .

[23]  M.J.M. Pelgrom,et al.  Matching properties of MOS transistors , 1989 .

[24]  M. A. Styblinski,et al.  Design for circuit quality: yield maximization, minimax, and Taguchi approach , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[25]  Peter Feldmann,et al.  Accurate and efficient evaluation of circuit yield and yield gradients , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[26]  Stephen W. Director,et al.  A new methodology for the design centering of IC fabrication processes , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[27]  A. R. Boothroyd,et al.  MISNAN-a physically based continuous MOSFET model for CAD applications , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[28]  Evert Seevinck,et al.  Current-mode techniques for high-speed VLSI circuits with application to current sense amplifier for CMOS SRAM's , 1991 .

[29]  K. Krishna,et al.  Optimization Of Parametric Yield: A Tutorial , 1992, 1992 Proceedings of the IEEE Custom Integrated Circuits Conference.

[30]  M. V. Fischetti,et al.  Monte Carlo simulation of a 30 nm dual-gate MOSFET: how short can Si go? , 1992, 1992 International Technical Digest on Electron Devices Meeting.

[31]  J. Purviance,et al.  Statistical performance sensitivity-a valuable measure for manufacturing oriented CAD , 1992, 1992 IEEE Microwave Symposium Digest MTT-S.

[32]  K. F. Lee,et al.  Scaling the Si MOSFET: from bulk to SOI to bulk , 1992 .

[33]  T. Vogelsang,et al.  Electron transport in strained Si layers on Si1−xGex substrates , 1993 .

[34]  John R. Koza,et al.  Genetic programming - on the programming of computers by means of natural selection , 1993, Complex adaptive systems.

[35]  K. Suyama,et al.  MOSFET modeling for analog circuit CAD: Problems and prospects , 1993, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '93.

[36]  Kang L. Wang,et al.  High-mobility p-channel metal-oxide-semiconductor field-effect transistor on strained Si , 1993 .

[37]  D. Flandre,et al.  Modeling of ultrathin double-gate nMOS/SOI transistors , 1994 .

[38]  S. Takagi,et al.  On the universality of inversion layer mobility in Si MOSFET's: Part I-effects of substrate impurity concentration , 1994 .

[39]  J. C. Zhang Worst case design of digital integrated circuits , 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.

[40]  M. A. Styblinski,et al.  IC Variability Minimization using a New Cp and Cpk Based Variability/Performance Measure. , 1994 .

[41]  Kurt Antreich,et al.  Circuit analysis and optimization driven by worst-case distances , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[42]  Dominique Savignac,et al.  Unified complete MOSFET model for analysis of digital and analog circuits , 1994, ICCAD '94.

[43]  J. Welser,et al.  Strain dependence of the performance enhancement in strained-Si n-MOSFETs , 1994, Proceedings of 1994 IEEE International Electron Devices Meeting.

[44]  Zhihua Wang,et al.  An efficient yield optimization method using a two step linear approximation of circuit performance , 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.

[45]  E. Vittoz,et al.  An analytical MOS transistor model valid in all regions of operation and dedicated to low-voltage and low-current applications , 1995 .

[46]  S.G. Duvall,et al.  A practical methodology for the statistical design of complex logic products for performance , 1995, IEEE Trans. Very Large Scale Integr. Syst..

[47]  Jan M. Rabaey,et al.  Digital Integrated Circuits: A Design Perspective , 1995 .

[48]  Sung-Mo Kang,et al.  Worst-case analysis and optimization of VLSI circuit performances , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[49]  Satoshi Shigematsu,et al.  A 1-V multithreshold-voltage CMOS digital signal processor for mobile phone application , 1996, IEEE J. Solid State Circuits.

[50]  M. Redford,et al.  Analysis of mixed-signal manufacturability with statistical technology CAD (TCAD) , 1996 .

[51]  S. Laux,et al.  Band structure, deformation potentials, and carrier mobility in strained Si, Ge, and SiGe alloys , 1996 .

[52]  J. Hauser,et al.  Extraction of experimental mobility data for MOS devices , 1996 .

[53]  Satoshi Shigematsu,et al.  A 1-V high-speed MTCMOS circuit scheme for power-down application circuits , 1997, IEEE J. Solid State Circuits.

[54]  J.J. Welser,et al.  Hole mobility improvement in silicon-on-insulator and bulk silicon transistors using local strain , 1997, International Electron Devices Meeting. IEDM Technical Digest.

[55]  Y. Taur,et al.  Quantum-mechanical modeling of electron tunneling current from the inversion layer of ultra-thin-oxide nMOSFET's , 1997, IEEE Electron Device Letters.

[56]  R. van Langevelde,et al.  Effect of gate-field dependent mobility degradation on distortion analysis in MOSFETs , 1997 .

[57]  Young,et al.  Dual Threshold Voltages And Substrate Bias: Keys To High Performance, Low Power, 0.1 /spl mu/m Logic Designs , 1997, 1997 Symposium on VLSI Technology.

[58]  G. Debyser,et al.  Efficient analog circuit synthesis with simultaneous yield and robustness optimization , 1998, 1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287).

[59]  Bharadwaj Amrutur,et al.  A replica technique for wordline and sense control in low-power SRAM's , 1998, IEEE J. Solid State Circuits.

[60]  Mark C. Johnson,et al.  Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks , 1998, ISLPED '98.

[61]  Yuan Taur,et al.  Fundamentals of Modern VLSI Devices , 1998 .

[62]  K. Rim,et al.  Transconductance enhancement in deep submicron strained Si n-MOSFETs , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

[63]  H. Momose,et al.  A 60 mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme , 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).

[64]  Vivek De,et al.  Technology and design challenges for low power and high performance [microprocessors] , 1999, Proceedings. 1999 International Symposium on Low Power Electronics and Design (Cat. No.99TH8477).

[65]  Narain D. Arora Modeling and Characterization of Ultra Deep Submicron CMOS Devices , 1999 .

[66]  Chenming Hu,et al.  Sub 50-nm FinFET: PMOS , 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

[67]  M.A. Horowitz,et al.  Speed and power scaling of SRAM's , 2000, IEEE Journal of Solid-State Circuits.

[68]  S. Nassif,et al.  Delay variability: sources, impacts and trends , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

[69]  K. Tanaka,et al.  Level converters with high immunity to power-supply bouncing for high-speed sub-1-V LSIs , 2000, 2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103).

[70]  Changbum Im,et al.  Designing built-in self-test circuits for embedded memories test , 2000, Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434).

[71]  C. Hu,et al.  FinFET-a self-aligned double-gate MOSFET scalable to 20 nm , 2000 .

[72]  G. Dewey,et al.  30 nm physical gate length CMOS transistors with 1.0 ps n-MOS and 1.7 ps p-MOS gate delays , 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

[73]  Luca Benini,et al.  A survey of design techniques for system-level dynamic power management , 2000, IEEE Trans. Very Large Scale Integr. Syst..

[74]  Takayasu Sakurai,et al.  Boosted gate MOS (BGMOS): device/circuit cooperation scheme to achieve leakage-free giga-scale integration , 2000, Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044).

[75]  S. Kumashiro,et al.  HiSIM: a drift-diffusion-based advanced MOSFET model for circuit simulation with easy parameter extraction , 2000, 2000 International Conference on Simulation Semiconductor Processes and Devices (Cat. No.00TH8502).

[76]  Sani R. Nassif Design for Variability in DSM Technologies , 2000 .

[77]  J. Bude,et al.  MOSFET modeling into the ballistic regime , 2000, 2000 International Conference on Simulation Semiconductor Processes and Devices (Cat. No.00TH8502).

[78]  D.B.M. Klaassen,et al.  RF-distortion in deep-submicron CMOS technologies , 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

[79]  Tomohiro Kubo,et al.  High-performance 80-nm gate length SOI-CMOS technology with copper and very-low-k interconnects , 2000, 2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104).

[80]  Michiel Steyaert,et al.  A layout-aware synthesis methodology for RF circuits , 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).

[81]  Mitiko Miura-Mattausch,et al.  MOSFET modeling gets physical , 2001 .

[82]  K. Soumyanath,et al.  Robustness of sub-70 nm dynamic circuits: analytical techniques and scaling trends , 2001, 2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185).

[83]  Vivek De,et al.  Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs , 2001, ISLPED '01.

[84]  T. Fuse,et al.  A 0.5 V power-supply scheme for low power LSIs using multi-Vt SOI CMOS technology , 2001, 2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185).

[85]  A. Gattiker,et al.  Timing yield estimation from static timing analysis , 2001, Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design.

[86]  J. Meindl,et al.  The impact of intrinsic device fluctuations on CMOS SRAM cell stability , 2001, IEEE J. Solid State Circuits.

[87]  Yuan Taur,et al.  Device scaling limits of Si MOSFETs and their application dependencies , 2001, Proc. IEEE.

[88]  B. Wicht,et al.  Analysis and compensation of the bitline multiplexer in SRAM current sense amplifiers , 2001 .

[89]  A. Chatterjee,et al.  Dual-threshold voltage assignment with transistor sizing for low power CMOS circuits , 2001, IEEE Trans. Very Large Scale Integr. Syst..

[90]  David Blaauw,et al.  Drowsy caches: simple techniques for reducing leakage power , 2002, ISCA.

[91]  K. Ishibashi,et al.  0.4-V logic library friendly SRAM array using rectangular-diffusion cell and delta-boosted-array-voltage scheme , 2002, 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).

[92]  James D. Meindl,et al.  Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration , 2002, IEEE J. Solid State Circuits.

[93]  Willy Sansen,et al.  An easy-to-use mismatch model for the MOS transistor , 2002, IEEE J. Solid State Circuits.

[94]  James Kao,et al.  Subthreshold leakage modeling and reduction techniques , 2002, ICCAD 2002.

[95]  R. Degraeve,et al.  Understanding nMOSFET Characteristics after Soft Breakdown and Their Dependence on the Breakdown Location , 2002, 32nd European Solid-State Device Research Conference.

[96]  Yuan Taur,et al.  Design considerations for CMOS near the limits of scaling , 2002 .

[97]  David Blaauw,et al.  Modeling and analysis of leakage power considering within-die process variations , 2002, ISLPED '02.

[98]  Colin Rose,et al.  Mathematical Statistics with Mathematica , 2002 .

[99]  A. Alvandpour,et al.  High-performance and low-power challenges for sub-70 nm microprocessor circuits , 2002, Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285).

[100]  P. Bai,et al.  A 90 nm logic technology featuring 50 nm strained silicon channel transistors, 7 layers of Cu interconnects, low k ILD, and 1 /spl mu/m/sup 2/ SRAM cell , 2002, Digest. International Electron Devices Meeting,.

[101]  Hiroshi Kawaguchi,et al.  VTH-hopping scheme to reduce subthreshold leakage for low-power processors , 2002, IEEE J. Solid State Circuits.

[102]  Yuan Taur,et al.  CMOS design near the limit of scaling , 2002 .

[103]  Bin Yu,et al.  FinFET scaling to 10 nm gate length , 2002, Digest. International Electron Devices Meeting,.

[104]  Atila Alvandpour,et al.  A sub-130-nm conditional keeper technique , 2002, IEEE J. Solid State Circuits.

[105]  H.-S. Philip Wong Beyond the conventional transistor , 2002, IBM J. Res. Dev..

[106]  Saibal Mukhopadhyay,et al.  Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits , 2003, Proc. IEEE.

[107]  Atila Alvandpour,et al.  High-performance and low-voltage sense-amplifier techniques for sub-90nm SRAM , 2003, IEEE International [Systems-on-Chip] SOC Conference, 2003. Proceedings..

[108]  Kaushik Roy,et al.  Modeling and estimation of total leakage current in nano-scaled CMOS devices considering the effect of parameter variation , 2003, ISLPED '03.

[109]  Sachin S. Sapatnekar,et al.  Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal , 2003, ICCAD 2003.

[110]  M. Romeo,et al.  Broad distribution effects in sums of lognormal random variables , 2002, physics/0211065.

[111]  David Blaauw,et al.  Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations , 2003, ICCAD 2003.

[112]  T. Nirschl,et al.  A yield-optimized latch-type SRAM sense amplifier , 2003, ESSCIRC 2004 - 29th European Solid-State Circuits Conference (IEEE Cat. No.03EX705).

[113]  Chenming Hu,et al.  A 65nm node strained SOI technology with slim spacer , 2003, IEEE International Electron Devices Meeting 2003.

[114]  N. Planes,et al.  Thin oxynitride solution for digital and mixed-signal 65nm CMOS platform , 2003, IEEE International Electron Devices Meeting 2003.

[115]  S.Y. Han,et al.  Static noise margin of the full DG-CMOS SRAM cell using bulk FinFETs (Omega MOSFETs) , 2003, IEEE International Electron Devices Meeting 2003.

[116]  Chandramouli V. Kashyap,et al.  Block-based static timing analysis with uncertainty , 2003, ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486).

[117]  Ying Zhang,et al.  Extension and source/drain design for high-performance FinFET devices , 2003 .

[118]  B Wicht Current sense amplifiers for embedded SRAM in high-performance system-on-a-chip designs , 2003 .

[119]  T. Sakurai Perspectives on power-aware electronics , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[120]  A. Ogura,et al.  Sub-10-nm planar-bulk-CMOS devices using lateral junction control , 2003, IEEE International Electron Devices Meeting 2003.

[121]  B. Wicht,et al.  A 1.5V 1.7ns 4k /spl times/ 32 SRAM with a fully-differential auto-power-down current sense amplifier , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[122]  D. Schroder,et al.  Negative bias temperature instability: Road to cross in deep submicron silicon semiconductor manufacturing , 2003 .

[123]  Takayasu Sakurai,et al.  Optimum Device Consideration for Standby Power Reduction Scheme Using Drain-Induced Barrier Lowering , 2003 .

[124]  Georges G. E. Gielen,et al.  Simulation-based generation of posynomial performance models for the sizing of analog integrated circuits , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[125]  R. Heald,et al.  Variability in sub-100nm SRAM designs , 2004, ICCAD 2004.

[126]  Jan M. Rabaey,et al.  SRAM leakage suppression by minimizing standby supply voltage , 2004, International Symposium on Signals, Circuits and Systems. Proceedings, SCS 2003. (Cat. No.03EX720).

[127]  Kaustav Banerjee,et al.  Subthreshold leakage power distribution considering within-die and die-to-die P-T-V variations , 2004, Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758).

[128]  Michael Orshansky,et al.  Fast statistical timing analysis handling arbitrary delay correlations , 2004, Proceedings. 41st Design Automation Conference, 2004..

[129]  David Blaauw,et al.  Circuit and microarchitectural techniques for reducing cache leakage power , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[130]  S. Roy,et al.  The impact of random doping effects on CMOS SRAM cell , 2004, Proceedings of the 30th European Solid-State Circuits Conference.

[131]  Statistical optimization of leakage power considering process variations using dual-Vth and sizing , 2004, Proceedings. 41st Design Automation Conference, 2004..

[132]  Hugues Bersini,et al.  Constrained, non-linear, derivative-free, parallel optimization of continuous, high computing load, noisy objective functions , 2004 .

[133]  A. Asenov,et al.  Scaling study of Si and strained Si n-MOSFETs with different high-k gate stacks , 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

[134]  David Blaauw,et al.  Parametric yield estimation considering leakage variability , 2004, Proceedings. 41st Design Automation Conference, 2004..

[135]  M. Ieong,et al.  Aggressively scaled (0.143 /spl mu/m/sup 2/) 6T-SRAM cell for the 32 nm node and beyond , 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

[136]  K. Roy,et al.  Modeling and estimation of failure probability due to parameter variations in nano-scale SRAMs for yield enhancement , 2004, 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525).

[137]  David Blaauw,et al.  Making typical silicon matter with Razor , 2004, Computer.

[138]  R. Rooyackers,et al.  A 0.314/spl mu/m/sup 2/ 6T-SRAM cell build with tall triple-gate devices for 45nm applications using 0.75NA 193nm lithography , 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

[139]  Noel Menezes,et al.  Statistical timing analysis based on a timing yield model , 2004, Proceedings. 41st Design Automation Conference, 2004..

[140]  M. Woo,et al.  Low cost 65nm CMOS platform for Low Power & General Purpose applications , 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..

[141]  S. Kosonocky,et al.  A transregional CMOS SRAM with single, logic V/sub DD/ and dynamic power rails , 2004, 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525).

[142]  Karen Maex,et al.  Interconnect width selection for deep submicron designs using the table lookup method , 2004, SLIP '04.

[143]  T. Nirschl,et al.  Yield and speed optimization of a latch-type voltage sense amplifier , 2004, IEEE Journal of Solid-State Circuits.

[144]  Wayne P. Burleson,et al.  Sensing design issues in deep submicron CMOS SRAMs , 2005, IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05).

[145]  Georges G. E. Gielen,et al.  CAFFEINE: template-free symbolic model generation of analog circuits via canonical form functions and genetic programming , 2005, Design, Automation and Test in Europe.

[146]  S. Shimada,et al.  Low-power embedded SRAM modules with expanded margins for writing , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[147]  Georges G. E. Gielen,et al.  Performance space modeling for hierarchical synthesis of analog integrated circuits , 2005, Proceedings. 42nd Design Automation Conference, 2005..

[148]  W. Dehaene,et al.  A yield-aware modeling methodology for nano-scaled SRAM designs , 2005, 2005 International Conference on Integrated Circuit Design and Technology, 2005. ICICDT 2005..

[149]  K. Itoh Low-voltage embedded RAMs in the nanometer era , 2005, 2005 International Conference on Integrated Circuit Design and Technology, 2005. ICICDT 2005..

[150]  Kaushik Roy,et al.  Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[151]  C. Wann,et al.  SRAM cell design for stability methodology , 2005, IEEE VLSI-TSA International Symposium on VLSI Technology, 2005. (VLSI-TSA-Tech)..

[152]  Willy Sansen,et al.  Matching Properties of Deep Sub-Micron MOS Transistors , 2005 .

[153]  B.C. Paul,et al.  Process variation in embedded memories: failure analysis and variation aware architecture , 2005, IEEE Journal of Solid-State Circuits.

[154]  Georges G. E. Gielen,et al.  IBMG: interpretable behavioral model generator for nonlinear analog circuits via canonical form functions and genetic programming , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[155]  Hua Wang,et al.  Variable tapered pareto buffer design and implementation allowing run-time configuration for low-power embedded SRAMs , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[156]  Georges G. E. Gielen,et al.  Analysis of simulation-driven numerical performance modeling techniques for application to analog circuit optimization , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[157]  Zsolt Tokei,et al.  Reliability challenges for copper low-k dielectrics and copper diffusion barriers , 2005, Microelectron. Reliab..

[158]  J.J. Liaw,et al.  The design, analysis, and development of highly manufacturable 6-T SRAM bitcells for SoC applications , 2005, IEEE Transactions on Electron Devices.

[159]  J. Michelon,et al.  The impact of scaling on interconnect reliability , 2005, 2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual..

[160]  K. Takeda,et al.  A read-static-noise-margin-free SRAM cell for low-V/sub dd/ and high-speed applications , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[161]  R. Rooyackers,et al.  Integration of tall triple-gate devices with inserted-Ta/sub x/N/sub y/ gate in a 0.274/spl mu/m/sup 2/ 6T-SRAM cell and advanced CMOS logic circuits , 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

[162]  Chandramouli Visweswariah,et al.  Statistical Timing for Parametric Yield Prediction of Digital Integrated Circuits , 2003, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[163]  W. Dehaene,et al.  Read Stability and Write-Ability Analysis of SRAM Cells for Nanometer Technologies , 2006, IEEE Journal of Solid-State Circuits.

[164]  Adhemar Bultheel Inleiding tot de numerieke wiskunde , 2006 .

[165]  K. Ravindran,et al.  First-Order Incremental Block-Based Statistical Timing Analysis , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[166]  Akira Matsuzawa,et al.  Fully-Depleted SOI CMOS Circuits and Technology for Ultralow-Power Applications , 2006 .

[167]  Wim Dehaene,et al.  A Low Power Embedded SRAM for Wireless Applications , 2006 .

[168]  Antonios Papanikolaou Application-driven software configuration of communication networks and memory organizations , 2006 .

[169]  Philippe Roussel,et al.  Gate oxide breakdown in FET devices and circuits: From nanoscale physics to system-level reliability , 2007, Microelectron. Reliab..