Efficient selection and analysis of critical-reliability paths and gates

Aging effects such as negative bias temperature instability (NBTI) and hot carrier injection (HCI) have become major concerns when designing reliable circuits at sub-45nm technologies. It is vital to efficiently identify the paths that age at a faster rate than others in the field. Moreover, gates having the most impact on the degradation of these paths must be identified for compensation purposes. In this paper, we propose (i) a new timing analysis flow, which can quickly and accurately predict path and gate degradation due to NBTI and HCI effects, and (ii) a novel algorithm that can effectively identify the smallest set of critical-reliability gates while quantitatively evaluates their relative importance to path delay degradation. This facilitates reliability-enhancement methods to efficiently mitigate reliability threats using minimum area overhead. Our simulation results on several benchmark circuits demonstrate the efficiency of the proposed technique.

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