Technique to Reduce the Resolution Requirement of Digitally Controlled Oscillators for Digital PLLs

Phase-locked loops (PLLs) are a critical component in modern systems. Digital PLLs (DPLLs) are increasingly popular in CMOS technologies due to their ease of integration and scalability with digital logic. However, digital quantization results in larger steady-state systematic jitter, or dithering. High resolution is needed to control the oscillator to minimize the dithering. This brief proposes a simple method to reduce the frequency-resolution requirement. The method allows for substantial reduction in the hardware complexity without sacrificing the DPLL's dynamic characteristics

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