Lessons learned: How to Make Predictable PCB Interconnects for Data Rates of 50 Gbps and Beyond

Design of PCB interconnects for data channels running at bitrate 50 Gbps and beyond is a very challenging problem that requires analyses and measurements over extremely broad frequency bandwidth from DC to 50 GHz and above. This paper shares our experience in building a practical methodology to make predictable 50 Gbps interconnects models. Substantial part of interconnects can be simulated with transmission line models that require identification of causal broadband dielectric and conductor roughness models. It is shown that separation of losses between the conductor roughness and dielectric models is essential element of such identification. Examples of proper and improper material models identification and consequences are provided in the paper. Accurate prediction of interconnect behavior also requires localization and 3D EM analysis for all transitions or discontinuities. Examples of optimized interconnects designed for 50 Gbps channels and the validation with measurements are also provided.