Hierarchical memory system design for a heterogeneous multi-core processor

Multi-core architecture has become hot issue recently both for performance and power consideration. Memory system is the bottleneck under this circumstance. A multi-core architecture using simple cores based on transport triggered architecture is proposed. This architecture has a uniform programming view. The memory system design exploration and optimization is done and a hierarchical memory system is designed. A balanced memory bandwidth is provided to the multi-core architecture.

[1]  Li Shen,et al.  A New Architecture For Multiple-Precision Floating-Point Multiply-Add Fused Unit Design , 2007, 18th IEEE Symposium on Computer Arithmetic (ARITH '07).

[2]  Norman P. Jouppi,et al.  Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction , 2003, MICRO.

[3]  William J. Dally,et al.  Memory hierarchy design for stream computing , 2005 .

[4]  Richard E. Matick,et al.  Logic-based eDRAM: Origins and rationale for use , 2005, IBM J. Res. Dev..

[5]  Miodrag Potkonjak,et al.  MediaBench: a tool for evaluating and synthesizing multimedia and communications systems , 1997, Proceedings of 30th Annual International Symposium on Microarchitecture.

[6]  Kunle Olukotun,et al.  The Stanford Hydra CMP , 2000, IEEE Micro.

[7]  J. P. Grossman.  A Systolic Array for Implementing LRU Replacement , 2002 .

[8]  Mahmut T. Kandemir,et al.  Generating physical addresses directly for saving instruction TLB energy , 2002, MICRO.

[9]  H. Peter Hofstee,et al.  Power efficient processor architecture and the cell processor , 2005, 11th International Symposium on High-Performance Computer Architecture.

[10]  Henk Corporaal,et al.  MOVE: a framework for high-performance processor design , 1991, Proceedings of the 1991 ACM/IEEE Conference on Supercomputing (Supercomputing '91).

[11]  Tomás Lang,et al.  Reducing TLB power requirements , 1997, Proceedings of 1997 International Symposium on Low Power Electronics and Design.

[12]  Guang R. Gao,et al.  TiNy threads: a thread virtual machine for the Cyclops64 cellular architecture , 2005, 19th IEEE International Parallel and Distributed Processing Symposium.

[13]  Zhiying Wang,et al.  A Heterogeneous Multi-core Processor Architecture for High Performance Computing , 2006, Asia-Pacific Computer Systems Architecture Conference.

[14]  Kenneth M. Wilson,et al.  Designing High Bandwidth On-chip Caches , 1997, Conference Proceedings. The 24th Annual International Symposium on Computer Architecture.

[15]  Norman P. Jouppi,et al.  Single-ISA heterogeneous multi-core architectures for multithreaded workload performance , 2004, Proceedings. 31st Annual International Symposium on Computer Architecture, 2004..