Refresh frequency reduction of data stored in SSDs based on A-timer and timestamps
暂无分享,去创建一个
Luigi Dilillo | Emna Farjallah | Jean-Marc Armani | Valentin Gherman | Emna Chabchoub | Franck Badets | Costin Anghel | Marcelino Seif | Christophe Layer | Francis Joffre | C. Anghel | J. Armani | F. Joffre | F. Badets | L. Dilillo | V. Gherman | Christophe Layer | Marcelino Seif | Emna Farjallah | E. Chabchoub
[1] Myounggon Kang,et al. Activation Energies $(E_{a})$ of Failure Mechanisms in Advanced NAND Flash Cells for Different Generations and Cycling , 2013, IEEE Transactions on Electron Devices.
[2] Paolo Prinetto,et al. FLARES: An Aging Aware Algorithm to Autonomously Adapt the Error Correction Capability in NAND Flash Memories , 2014, ACM Trans. Archit. Code Optim..
[3] Anastasia Ailamaki,et al. Improving Flash Write Performance by Using Update Frequency , 2013, Proc. VLDB Endow..
[4] Onur Mutlu,et al. ERRoR ANAlysIs AND RETENTIoN-AwARE ERRoR MANAgEMENT FoR NAND FlAsh MEMoRy , 2013 .
[5] William R. Reohr,et al. Memories: Exploiting Them and Developing Them , 2006, 2006 IEEE International SOC Conference.
[6] Tong Zhang,et al. Quasi-nonvolatile SSD: Trading flash memory nonvolatility to improve storage system performance for enterprise applications , 2012, IEEE International Symposium on High-Performance Comp Architecture.
[7] P. Kalavade,et al. Flash EEPROM threshold instabilities due to charge trapping during program/erase cycling , 2004, IEEE Transactions on Device and Materials Reliability.
[8] How Micron. The Challenges of Scaling Nonvolatile Memory in Embedded Systems , 2013 .
[9] J. Kessenich,et al. Bit error rate in NAND Flash memories , 2008, 2008 IEEE International Reliability Physics Symposium.
[10] Jongmoo Choi,et al. WARM: Improving NAND flash memory lifetime with write-hotness aware retention management , 2015, 2015 31st Symposium on Mass Storage Systems and Technologies (MSST).
[11] Joseph Yiu,et al. The definitive guide to the ARM Cortex-M3 , 2007 .
[12] Richard Veras,et al. RAIDR: Retention-aware intelligent DRAM refresh , 2012, 2012 39th Annual International Symposium on Computer Architecture (ISCA).
[13] Paolo Prinetto,et al. Performance and Reliability Analysis of Cross-Layer Optimizations of NAND Flash Controllers , 2015, ACM Trans. Embed. Comput. Syst..
[14] Qiang Wu,et al. A Large-Scale Study of Flash Memory Failures in the Field , 2015, SIGMETRICS 2015.
[15] Li-Pin Chang,et al. Hybrid solid-state disks: Combining heterogeneous NAND flash in large SSDs , 2008, 2008 Asia and South Pacific Design Automation Conference.
[16] Trevor N. Mudge,et al. Improving NAND Flash Based Disk Caches , 2008, 2008 International Symposium on Computer Architecture.
[17] Osman S. Unsal,et al. Flash correct-and-refresh: Retention-aware error management for increased flash memory lifetime , 2012, 2012 IEEE 30th International Conference on Computer Design (ICCD).
[18] Onur Mutlu,et al. Data retention in MLC NAND flash memory: Characterization, optimization, and recovery , 2015, 2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA).
[19] Chung H. Lam,et al. Storage Class Memory , 2010, 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology.