Binary and multi-valued SPFD-based wire removal in PLA networks

This paper describes the application of binary and multivalued SPFD-based wire removal techniques for circuit implementations utilizing networks of PLAs. It has been shown that a design style based on a multi-level network of approximately equal-sized PLAs results in a dense, fast, and crosstalk-resistant layout. Wire removal is a technique where the total number of wires between individual circuit nodes is reduced, either by removing wires, or replacing them with other existing wires. Three separate wire removal experiments are performed. Either wire removal is invoked before clustering the original netlist into a network of PLAs, or after clustering, or both before and after clustering. For wire removal before clustering, binary SPFD-based wire removal is used. For wire removal after clustering, multi-valued SPFD-based wire removal is used since the multi-output PLAs can be viewed as multi-valued single output nodes. We demonstrate that these techniques are effective. The most effective approach is to perform wire removal both before and after clustering. Using these techniques, we obtain a reduction in placed and routed circuit area of about 11%. This reduction is significantly higher (about 20%) for the larger circuits we used in our experiments.

[1]  Robert K. Brayton,et al.  Algorithms for discrete function manipulation , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[2]  Hiroshi Sawada,et al.  A new method to express functional permissibilities for LUT based FPGAs and its applications , 1996, Proceedings of International Conference on Computer Aided Design.

[3]  Robert K. Brayton,et al.  Cross-talk immune VLSI design using a network of PLAs embedded in a regular layout fabric , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

[4]  Hiroshi Sawada,et al.  A new method to express functional permissibilities for LUT based FPGAs and its applications , 1996, ICCAD 1996.

[5]  Randal E. Bryant,et al.  Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.

[6]  Kevin J. Nowka,et al.  Design methodology for a 1.0 GHz microprocessor , 1998, Proceedings International Conference on Computer Design. VLSI in Computers and Processors (Cat. No.98CB36273).

[7]  Robert K. Brayton,et al.  Implementation and use of SPFDs in optimizing Boolean networks , 1998, ICCAD.

[8]  A. Sangiovanni-Vincentelli,et al.  The TimberWolf placement and routing package , 1985, IEEE Journal of Solid-State Circuits.

[9]  Kwang-Ting Cheng,et al.  Sequential logic optimization by redundancy addition and removal , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).

[10]  Shih-Chieh Chang,et al.  Layout Driven Logic Synthesis for FPGAs , 1994, 31st Design Automation Conference.

[11]  R. Brayton,et al.  SPFD-based Wire Removal in a Network of PLAs , 1999 .

[12]  Hamid Savoj,et al.  Don't cares in multi-level network optimization , 1992 .

[13]  Vaughn Betz,et al.  VPR: A new packing, placement and routing tool for FPGA research , 1997, FPL.

[14]  P. R. Stephan,et al.  SIS : A System for Sequential Circuit Synthesis , 1992 .

[15]  Robert K. Brayton,et al.  Don't cares and multi-valued logic network minimization , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).