ASAP7 predictive design kit development and cell design technology co-optimization: Invited paper

This work discusses the ASAP7 predictive process design kit (PDK) and associated standard cell library. The necessity for multi-patterning (MP) techniques at advanced nodes results in the standard cell and SRAM architecture becoming entangled with design rules, mandating design-technology co-optimization (DTCO). This paper discusses the DTCO process involving standard cell physical design. An assumption of extreme ultraviolet (EUV) lithography availability in the PDK allows bi-directional M1 geometries that are difficult with MP. Routing and power distribution schemes for self-aligned quadruple patterning (SAQP) friendly, high density standard cell based blocks are shown. Restrictive design rules are required and supported by the automated place and route (APR) setup. Supporting sub-20 nm dimensions with academic tool licenses is described. The APR (QRC techfile) extraction shows high correlation with the Calibre extraction deck. Finally, use of the PDK for academic coursework and research is discussed.

[1]  Diederik Verkest,et al.  Architectural strategies in standard-cell design for the 7 nm and beyond technology node , 2016 .

[2]  Diederik Verkest,et al.  Maintaining Moore’s law: enabling cost-friendly dimensional scaling , 2015, Advanced Lithography.

[3]  Shien-Yang Wu,et al.  A 16nm FinFET CMOS technology for mobile SoC and computing applications , 2013 .

[4]  Lars W. Liebmann,et al.  The daunting complexity of scaling to 7NM without EUV: pushing DTCO to the extreme , 2015, Advanced Lithography.

[5]  Lawrence T. Clark,et al.  Design flows and collateral for the ASAP7 7nm FinFET predictive process design kit , 2017, 2017 IEEE International Conference on Microelectronic Systems Education (MSE).

[6]  Ankita Dosi,et al.  Design technology co-optimization of back end of line design rules for a 7 nm predictive process design kit , 2017, 2017 18th International Symposium on Quality Electronic Design (ISQED).

[7]  Ankita Dosi,et al.  Systematic analysis of the timing and power impact of pure lines and cuts routing for multiple patterning , 2017, Advanced Lithography.

[8]  Lawrence T. Clark,et al.  Robust 7-nm SRAM design on a predictive PDK , 2017, 2017 IEEE International Symposium on Circuits and Systems (ISCAS).

[9]  William Rhett Davis,et al.  FreePDK15: An Open-Source Predictive Process Design Kit for 15nm FinFET Technology , 2015, ISPD.

[10]  Sascha Migura,et al.  EUV lithography scanner for sub-8nm resolution , 2015, Advanced Lithography.

[11]  Bernhard Kneer,et al.  Imaging performance of EUV lithography optics configuration for sub-9nm resolution , 2015, Advanced Lithography.

[12]  Geert Vandenberghe,et al.  The economic impact of EUV lithography on critical process modules , 2014, Advanced Lithography.

[13]  Paul D. Franzon,et al.  FreePDK: An Open-Source Variation-Aware Design Kit , 2007, 2007 IEEE International Conference on Microelectronic Systems Education (MSE'07).

[14]  Xiaoqing Xu,et al.  Standard cell library design and optimization methodology for ASAP7 PDK: (Invited paper) , 2017, 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[15]  Saurabh Sinha,et al.  ASAP7: A 7-nm finFET predictive process design kit , 2016, Microelectron. J..

[16]  E. Babayan,et al.  32/28nm Educational Design Kit: Capabilities, deployment and future , 2013, 2013 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia).