An on-chip delay measurements module for nanostructures characterization
暂无分享,去创建一个
[1] P. J. Burke. An RF circuit model for carbon nanotubes , 2003 .
[2] Y. Savaria,et al. Time delay measurement methods for integrated transmission lines and high speed cell characterization , 1997, Proceedings of 1997 IEEE International Symposium on Circuits and Systems. Circuits and Systems in the Information Age ISCAS '97.
[3] Hans G. Kerkhoff,et al. On-chip tap-delay measurements for a digital delay-line used in high-speed inter-chip data communications , 2002, Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02)..
[4] Herbert Shea,et al. Single- and multi-wall carbon nanotube field-effect transistors , 1998 .
[5] Mircea R. Stan,et al. A Case for CMOS/nano co-design , 2002, ICCAD 2002.
[6] Keith A. Jenkins,et al. Measurement and modeling of on-chip transmission line effects in a 400 MHz microprocessor , 1998, IEEE J. Solid State Circuits.
[7] Krishnamurthy Soumyanath,et al. Accurate on-chip interconnect evaluation: a time-domain technique , 1999 .
[8] Jeffrey Bokor,et al. Monolithic Integration of Carbon Nanotube Devices with Silicon MOS Technology , 2004 .