A novel high speed Low Latency Column Bit Compressed MAC architecture for Wireless Sensor Network applications

Abstract Wireless Sensor Network (WSN) provides significant challenges for application such as distributed control and digital signal processing. Multiply-Accumulate Unit (MAC) plays a significant role in kernel computation which determines the speed and power factor of entire system. Constructing low power and high speed MAC is very critical to utilize VLSI technologies in WSN. This research work concentrates on fast, low power and reduced delay based Low Latency Column Bit Compressed (LLCBC) MAC. This proposed MAC design based on binary stacking counter is designed for optimizing delay, power, area and hardware complexities. Increased operational speed is attained by performing 6:3 and 7:3 binary stacking counters with higher column indeed of conventional full adder. The proposed method is simulated using cadence environment, in which superior outcomes are attained. The parameters such as Area, Cells, leakage power (nW), Dynamic Power (nW), Total Power (nW) and Delay (ps) are evaluated. For instance, in 16 bit, the proposed (LLCBC) MAC consumes 14.4% Area, 17.5% Total Power and 46.2% Delay with respect to maximum value among all MAC units compared. The proposed architecture is simulated, synthesized and place & route is done with 90 nm standard CMOS library using cadence SOC encounter, effectual improvement in terms of Power, Area, and Delay is attained.