Modeling the Effect of Redundancy on Yield and Performance of VLSI Systems

The incorporation of different forms of redundancy has been recently proposed for various VLSI and WSI designs. These include regular architectures, built by interconnecting a large number of a few types of system elements on a single chip or wafer. The motivation for introducing fault-tolerance (redundancy) into these architectures is two-fold: yield enhancement and performance (like computational availability) improvement.

[1]  Donald S. Fussell,et al.  Fault-tolerant wafer-scale architectures for VLSI , 1982, ISCA 1982.

[2]  Frank Thomson Leighton,et al.  Wafer-scale integration of systolic arrays , 1982, 23rd Annual Symposium on Foundations of Computer Science (sfcs 1982).

[3]  Arnold L. Rosenberg,et al.  The Diogenes Approach to Testable Fault-Tolerant Arrays of Processors , 1983, IEEE Transactions on Computers.

[4]  Vishwani D. Agrawal,et al.  Characterizing the LSI Yield Equation from Wafer Test Data , 1984, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[5]  C.H. Stapper,et al.  Integrated circuit yield statistics , 1983, Proceedings of the IEEE.

[6]  Melvin A. Breuer,et al.  On Area and Yield Considerations for Fault-Tolerant VLSI Processor Arrays , 1984, IEEE Transactions on Computers.

[7]  Lawrence Snyder,et al.  Introduction to the configurable, highly parallel computer , 1982, Computer.

[8]  Marco Ajmone Marsan,et al.  Markov Models for Multiple Bus Multiprocessor Systems , 1982, IEEE Transactions on Computers.

[9]  Algirdas Avizienis,et al.  Fault-Tolerant Design for VLSI: Effect of Interconnect Requirements on Yield Improvement of VLSI Designs , 1982, IEEE Transactions on Computers.

[10]  R. Wadsack.  Fault coverage in digital integrated circuits , 1978, The Bell System Technical Journal.

[11]  Israel Koren,et al.  Evaluating the Cost-Effectiveness of Switches in Processor Array Architectures , 1985, ICPP.

[12]  Peter J. Varman,et al.  Fault-tolerant wafer-scale architectures for VLSI , 1982, ISCA '82.

[13]  C. H. Stapper,et al.  Yield Model for Productivity Optimization of VLSI Memory Chips with Redundancy and Partially Good Product , 1980, IBM J. Res. Dev..

[14]  H. T. Kung,et al.  Fault-Tolerance and Two-Level Pipelining in VLSI Systolic Arrays , 1983 .

[15]  Israel Koren,et al.  Restructuring hexagonal arrays of processors in the presence of faults , 1987 .

[16]  R.P. Cenker,et al.  A fault-tolerant 64K dynamic random-access memory , 1979, IEEE Transactions on Electron Devices.

[17]  Donald F. Towsley,et al.  Approximate Models of Multiple Bus Multiprocessor Systems , 1986, IEEE Transactions on Computers.

[18]  Kye Sherrick Hedlund.  Wafer scale integration of configurable, highly parallel processors , 1982 .

[19]  Abbas El Gamal,et al.  Configuration of VLSI Arrays in the Presence of Defects , 1984, JACM.

[20]  Israel Koren.  A reconfigurable and fault-tolerant VLSI multiprocessor array , 1981, ISCA '81.

[21]  Lawrence Snyder,et al.  Wafer scale integration of Configurable, Highly Parallel (CHiP) processors , 1982, International Conference on Parallel Processing.