Artificial neural networks on a reconfigurable, fault-tolerant, multi-processor system

Abstract The authors propose a parallel architecture for neural network (NN) simulation in which the processing elements, based on digital signal processors, communicate through a common bus structure. The architecture offers high processing power and fault tolerance capabilities. These can be exploited by the use of dynamically reconfigurable devices in the communication interfaces. The architectural choices are discussed and a performance evaluation of the system is performed in order to assess its features.

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