VLSI array synthesis for polynomial GCD computation and application to finite field division
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[1] Sanjay V. Rajopadhye. Synthesizing systolic arrays with control signals from recurrence equations , 2005, Distributed Computing.
[2] Kiyomichi Araki,et al. Fast Inverters over Finite Field Based on Euclid's Algorithm , 1989 .
[3] Trieu-Kien Truong,et al. VLSI Architectures for Computing Multiplications and Inverses in GF(2m) , 1983, IEEE Transactions on Computers.
[4] Wayne P. Burleson,et al. Distributed control synthesis for data-dependent iterative algorithms , 1994, Proceedings of IEEE International Conference on Application Specific Array Processors (ASSAP'94).
[5] Chin-Liang Wang,et al. Systolic array implementation of multipliers for finite fields GF(2/sup m/) , 1991 .
[6] Irving S. Reed,et al. On the VLSI Design of a Pipeline Reed-Solomon Decoder Using Systolic Arrays , 1988, IEEE Trans. Computers.
[7] H. T. Kung,et al. Systolic VLSI Arrays for Polynomial GCD Computation , 1984, IEEE Transactions on Computers.
[8] Po Tong. A 40-MHz encoder-decoder chip generated by a Reed-Solomon code compiler , 1990, IEEE Proceedings of the Custom Integrated Circuits Conference.
[9] E.F. Deprettere,et al. Regular processor arrays with data-dependent dependencies , 1993, Proceedings of IEEE Workshop on VLSI Signal Processing.
[10] Yongjin Jeong,et al. VLSI array synthesis for polynomial GCD computation , 1993, Proceedings of International Conference on Application Specific Array Processors (ASAP '93).