FPGA Realization of Secured Hash Algorithm with Parallel Architecture

Now-a-days security is the main problem to transmit the information from one place to another. Hackers tries to get the information which is to be secured. So these attacks will be a problems for us and also a challenge. So there is need to provide the security for the information between different systems or networks. Hence for this Secure Hash Algorithm is introduced. Secure Hash Algorithm is the most widely used Hash function in the world. This is one of the cryptographic algorithm which is mainly used for security based applications. This algorithm provides the best security i.e., a message digest of size n produces a collision with a work factor of approximately 2^n/2. The algorithm takes the arbitrary length message as plain text and produces a fixed length message digest (Hash code) as cipher text. The algorithm has several functional blocks like compression function, round calculation etc. The round calculations in the SHA constitute several processing steps. These steps will be processed in a sequential manner. Because of sequential processing the time taken to compute round calculation will be more. So in order to reduce the computation time required for round calculation, instead of using sequential process here parallel process mechanism is applied. This will reduce the computation time for round calculation and hence increased the speed of operation the algorithm. Finally we compare the computation time for this algorithm with the existing one. Here the algorithm concept is implementing on sporton3 FPGA kit by using Verilog HDL.