Design and comparative analysis of low power 64 Bit SRAM and its peripherals using power reduction techniques

Today is the era of portable electronics where maximum functionality is embedded in the tiny chips. Advancement in deep submicron technology, has spurred the race of enhancing the number of transistors on VLSI chips. RAM and especially cache memory is considered to be the major part of any computing device, so power dissipation of memory is of major concern for VLSI design. Hence the major challenge is to design the memory cells which consume low power as compared to the conventional cells. Three various scheme are proposed in this paper for reduction of power in SRAM and these are Charge Recycling, Power Gating and low power design of peripherals. In this paper these techniques are implemented successfully on 45 nm technology. A 1/10th reduction in average power in sense amplifier design is achieved and power reduced in decoder design is 30.08%. Power reduction achieved for 64 bit SRAM using CR and MT scheme is 20.84%, 47.79% and 49.79% respectively for standby, read and write cycle.

[1]  Kaushik Roy,et al.  Low-Power CMOS VLSI Circuit Design , 2000 .

[2]  Lee-Sup Kim,et al.  A low power charge-recycling ROM architecture , 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

[3]  Bharadwaj Amrutur,et al.  Techniques to reduce power in fast wide memories [CMOS SRAMs] , 1994, Proceedings of 1994 IEEE Symposium on Low Power Electronics.

[4]  Bharadwaj Amrutur,et al.  Fast low-power decoders for RAMs , 2001, IEEE J. Solid State Circuits.

[5]  Ashok Sharma.  Semiconductor Memories Technology, Testing And Reliability , 2014 .

[6]  Satoshi Shigematsu,et al.  A shared-bitline SRAM cell architecture for 1-V ultra low-power word-bit configurable macrocells , 1999, Proceedings. 1999 International Symposium on Low Power Electronics and Design (Cat. No.99TH8477).

[7]  Yong-Bin Kim,et al.  Standby Leakage Power Reduction Technique for Nanoscale CMOS VLSI Systems , 2010, IEEE Transactions on Instrumentation and Measurement.

[8]  Lee-Sup Kim,et al.  A low-power SRAM using hierarchical bit line and local sense amplifiers , 2005, IEEE J. Solid State Circuits.

[9]  Neil Weste,et al.  Principles of CMOS VLSI Design , 1985 .

[10]  Ajay Kumar Singh,et al.  9T balanced SRAM cell for low power operation , 2009, 2009 IEEE Symposium on Industrial Electronics & Applications.

[11]  W. Dehaene,et al.  Read Stability and Write-Ability Analysis of SRAM Cells for Nanometer Technologies , 2006, IEEE Journal of Solid-State Circuits.

[12]  Ali Afzali-Kusha,et al.  Design and Analysis of Two Low-Power SRAM Cell Structures , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[13]  Lee-Sup Kim,et al.  A low-power charge-recycling ROM architecture , 2003, IEEE Trans. Very Large Scale Integr. Syst..

[14]  V. K. Singhal,et al.  64-bits low power CMOS SRAM by using 9T cell and charge recycling scheme , 2012, 2012 International Conference on Devices, Circuits and Systems (ICDCS).