A Design of Linearity Built-in Self-Test for Current-Steering DAC

In this paper, a current-mode Built-In Self-Test (BIST) scheme is proposed for on-chip estimating static non-linearity errors in current-steering digital-to-analog converters (DACs). The proposed DAC BIST scheme is designed to verify a 10-bit segmented current-steering DAC, consist of a 5-bit coarse DAC and a 5-bit fine one. This proposed BIST scheme includes a current-mode sample-and-difference circuit to increase the sampling current accuracy and control a current-controlled oscillator (ICO). In addition, only 36 measurements are required by using the selected-code method rather than 1024 measurements for the conventionally-utilized all-code method. Compared to the conventionally-utilized all-code method, about 85-% reduction of test time can be achieved.

[1]  Christofer Toumazou,et al.  Regulated Cascade Switched-Current Memory Cell , 1990 .

[2]  Soon-Jyh Chang,et al.  BIST scheme for DAC testing , 2002 .

[3]  K. Cheng,et al.  A BIST scheme for on-chip ADC and DAC testing , 2000, Proceedings Design, Automation and Test in Europe Conference and Exhibition 2000 (Cat. No. PR00537).

[4]  K. R. Lakshmikumar,et al.  Characterisation and modeling of mismatch in MOS transistors for precision analog design , 1986 .

[5]  Michiel Steyaert,et al.  Static and Dynamic Performance Limitations for High Speed D/A Converters , 2004 .

[6]  Vinita Vasudevan,et al.  A built-in-self-test scheme for digital to analog converters , 2004, 17th International Conference on VLSI Design. Proceedings..

[7]  E. A. Vittoz,et al.  Analysis and improvements of accurate dynamic current mirrors , 1990 .

[8]  Kcstcr The Data Conversion Handbook , 2007 .

[9]  Michiel Steyaert,et al.  Static and Dynamic Performance Limitations for High Speed D/a Converters (Kluwer International Series in Engineering and Computer Science, Secs 761.) , 2004 .

[10]  Yannis Tsividis,et al.  Current copier cells , 1988 .

[11]  Vinita Vasudevan,et al.  A Built-in-Self-Test Scheme for Segmented and Binary Weighted DACs , 2004, J. Electron. Test..

[12]  K. Arabi,et al.  A built-in self-test approach for medium to high-resolution digital-to-analog converters , 1994, Proceedings of IEEE 3rd Asian Test Symposium (ATS).

[13]  Bozena Kaminska,et al.  Testing digital to analog converters based on oscillation-test strategy using sigma-delta modulation , 1998, Proceedings International Conference on Computer Design. VLSI in Computers and Processors (Cat. No.98CB36273).

[14]  David A. Johns,et al.  Analog Integrated Circuit Design , 1996 .

[15]  Mohamad Sawan,et al.  On chip testing data converters using static parameters , 1998, IEEE Trans. Very Large Scale Integr. Syst..

[16]  M.J.M. Pelgrom,et al.  Matching properties of MOS transistors , 1989 .

[17]  David J. Allstot,et al.  Switched-current circuit design issues , 1991 .

[18]  Yun-Che Wen,et al.  BIST structure for DAC testing , 1998 .

[19]  Michiel Steyaert,et al.  An Accurate Statistical Yield Model for CMOS Current-Steering D/A Converters , 2001 .

[20]  Walt Kester,et al.  The data conversion handbook , 2005 .

[21]  Yannis Tsividis,et al.  Sampled-current circuits , 1989, IEEE International Symposium on Circuits and Systems,.

[22]  S. J. Daubert,et al.  Operation and analysis of current copier circuits , 1990 .

[23]  Gordon W. Roberts,et al.  An Introduction to Mixed-Signal IC Test and Measurement , 2000 .