Three-dimensional (3-D) wafer stacking technologies are receiving an increasing interest, even if it poses forward new challenges in the development of through silicon vias (TSVs) and thin wafer handling technologies. Several approaches have been developed these years for wafer separation. Even if many examples can be found in literature of the slide-off debonding use for TSVs applications, the thermoplastic materials required for this technique could be limiting for future 3D backside processes. Therefore, innovative room temperature debonding process, including special carrier treatment, has been recently developed to enable a vertical carrier/device separation on a dicing frame at room temperature. The purpose of this paper is to demonstrate the feasibility of this innovative temporary bonding technique and associated equipments. In a first time we have compared 3 temporary materials stability in a short loop process representative of critical backside integration steps. From these results we identify ...