Minimax and WLS Designs of Digital FIR Filters Using SOCP for Aliasing Errors Reduction in BI-DAC

This paper presented the optimal minimax and weighted least squares (WLS) methods for designing digital finite impulse response (FIR) filters to reduce the aliasing errors generated by the non-ideality of analog filters and mixers in bandwidth interleaving digital-to-analog converter (BI-DAC). To satisfy the given expected spurious free dynamic range (SFDR), we formulated these optimal designs of digital FIR filters in BI-DAC as a convex optimization problem—second-order cone programming (SOCP) that allowed the linear equality and convex quadratic inequality constraints including the magnitude flatness and the peak aliasing errors constraints to be merged. Furthermore, we derived the computational complexity of our presented optimal design. Several design examples were given to evaluate the performance of our presented unconstrained and constrained minimax and WLS designs using SOCP including their effectiveness and computational complexity. The simulation results showed that, in our presented unconstrained minimax and WLS designs using SOCP, the maximum distortion errors were all around 0.02 dB. The maximum aliasing errors were−73.9 and −80.5 dB, which satisfied the expected SFDR of a 12-bit BI-DAC system. In addition, we analyzed the influence of different values of the nonnegative weighting function on our presented unconstrained minimax and WLS designs using SOCP, and we found that there was a tradeoff among the nonnegative weighting function’s value, and the distortion and aliasing errors. Moreover, when the constraints were imposed in our presented constrained minimax and WLS designs using SOCP in the selected frequency bands, the distortion errors were equal to zero and the aliasing errors were reduced below −110 dB, but the expense was that the larger distortion and aliasing errors achieved out of these selected frequency bands. Finally, we gave the computational complexity comparisons among our presented unconstrained and constrained minimax and WLS design using SOCP, we also compared the influence of the digital FIR filters’ length on our presented designs’ worst-case passband ripple and stopband roll-off, and we found that there was a tradeoff among the digital FIR filters’ length, the passband ripple, the stopband roll-off, the computational complexity, and the actual hardware cost.

[1]  Kate A. Remley,et al.  Two-stage correction for wideband wireless signal generators with time-interleaved digital-to-analog-converters , 2014, 83rd ARFTG Microwave Measurement Conference.

[2]  S. Chandrasekhar,et al.  All-Electronic 100-GHz Bandwidth Digital-to-Analog Converter Generating PAM Signals up to 190 GBaud , 2016, Journal of Lightwave Technology.

[3]  Tian-Bo Deng Generalized WLS Method for Designing All-Pass Variable Fractional-Delay Digital Filters , 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.

[4]  Yu Hen Hu,et al.  Random Triggering-Based Sub-Nyquist Sampling System for Sparse Multiband Signal , 2017, IEEE Transactions on Instrumentation and Measurement.

[5]  Kuojun Yang,et al.  Digital correction of frequency-response errors in bandwidth-interleaved ADCs , 2016 .

[6]  Shulin Tian,et al.  Precisely synchronous and cascadable multi-channel arbitrary waveform generator. , 2017, The Review of scientific instruments.

[7]  Ke Liu,et al.  Minimax design of digital FIR filters using linear programming in bandwidth interleaving digital-to-analog converter , 2018, IEICE Electronics Express.

[8]  Graham A. Jullien,et al.  A linear programming approach to recursive digital filter design with linear phase , 1982 .

[9]  Volker Jungnickel,et al.  Enhancing the Bandwidth of DACs by Analog Bandwidth Interleaving , 2016 .

[10]  Volker Jungnickel,et al.  Digital signal splitting among multiple DACs for analog bandwidth interleaving (ABI) , 2016, 2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS).

[11]  Tian-Bo Deng,et al.  Decoupling Minimax Design of Low-Complexity Variable Fractional-Delay FIR Digital Filters , 2011, IEEE Transactions on Circuits and Systems I: Regular Papers.

[12]  Soo-Chang Pei,et al.  Two-Dimensional Farrow Structure and the Design of Variable Fractional-Delay 2-D FIR Digital Filters , 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.

[13]  Jong-Jy Shyu,et al.  Minimax phase error design of allpass variable fractional-delay digital filters by iterative weighted least-squares method , 2009, Signal Process..

[14]  C. Krall,et al.  Time-Interleaved Digital-to-Analog Converters for UWB Signal Generation , 2007, 2007 IEEE International Conference on Ultra-Wideband.

[15]  J. O. Coleman,et al.  Design of nonlinear-phase FIR filters with second-order cone programming , 1999, 42nd Midwest Symposium on Circuits and Systems (Cat. No.99CH36356).

[16]  Tian-Bo Deng,et al.  Hybrid Structures for Low-Complexity Variable Fractional-Delay FIR Filters , 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.

[17]  Chien-Cheng Tseng,et al.  Design of 1-D and 2-D variable fractional delay allpass filters using weighted least-squares method , 2002 .

[18]  Tian-Bo Deng Minimax Design of Low-Complexity Even-Order Variable Fractional-Delay Filters Using Second-Order Cone Programming , 2011, IEEE Transactions on Circuits and Systems II: Express Briefs.

[19]  Soo-Chang Pei,et al.  A generalized approach to the design of variable fractional-delay FIR digital filters , 2008, Signal Process..

[20]  H. Kwan,et al.  Minimax Design of IIR Digital Filters Using Iterative SOCP , 2010 .

[21]  Takao Hinamoto,et al.  Optimal design of FIR frequency-response-masking filters using second-order cone programming , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

[22]  Yang Xing,et al.  Synchronization method of multiple multiplexed DACs , 2017, 2017 13th IEEE International Conference on Electronic Measurement & Instruments (ICEMI).

[23]  Jie-Cherng Liu,et al.  Weighted least squares near-equiripple approximation of variable fractional delay FIR filters , 2007 .

[24]  Houjun Wang,et al.  Estimation and compensation methods of time delay and phase offset in hybrid filter bank DACs , 2018, Electronics Letters.