NoC topology synthesis for supporting shutdown of voltage islands in SoCs

In many systems on chips (SoCs), the cores are clustered in to voltage islands. When cores in an island are unused, the entire island can be shutdown to reduce the leakage power consumption. However, today, the interconnect architecture is a bottleneck in allowing the shutdown of the islands. In this paper, we present a synthesis approach to obtain customized application-specific networks on chips (NoCs) that can support the shutdown of voltage islands. Our results on realistic SoC benchmarks show that the resulting NoC designs only have a negligible overhead in SoC active power consumption (average of 3%) and area (average of 0.5%) to support the shutdown of islands. The shutdown support provided can lead to a significant leakage and hence total power savings.

[1]  Jens Sparsø,et al.  An OCP Compliant Network Adapter for GALS-based SoC Design Using the MANGO Network-on-Chip , 2005, 2005 International Symposium on System-on-Chip.

[2]  John M. Cohn,et al.  Managing power and performance for system-on-chip designs using Voltage Islands , 2002, IEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002..

[3]  L. Benini,et al.  Designing Application-Specific Networks on Chips with Floorplan Information , 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

[4]  Luca Benini,et al.  On-Chip Communication Architectures: System on Chip Interconnect , 2008 .

[5]  Evangeline F. Y. Young,et al.  Voltage island-driven floorplanning , 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

[6]  Srinivasan Murali,et al.  SUNMAP: a tool for automatic topology selection and generation for NoCs , 2004, Proceedings. 41st Design Automation Conference, 2004..

[7]  Federico Angiolini,et al.  /spl times/pipes Lite: a synthesis oriented design library for networks on chips , 2005, Design, Automation and Test in Europe.

[8]  Fabien Clermidy,et al.  Physical Implementation of the DSPIN Network-on-Chip in the FAUST Architecture , 2008, Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008).

[9]  Vincent John Mooney,et al.  Automated bus generation for multiprocessor SoC design , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[10]  Luca Benini,et al.  Multiple power-gating domain (multi-VGND) architecture for improved leakage power reduction , 2008, Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08).

[11]  Chi-Ying Tsui,et al.  Energy-Aware Synthesis of Networks-on-Chip Implemented with Voltage Islands , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[12]  Nikil D. Dutt,et al.  Floorplan-aware automated synthesis of bus-based communication architectures , 2005, Proceedings. 42nd Design Automation Conference, 2005..

[13]  Alain Greiner,et al.  A generic architecture for on-chip packet-switched interconnections , 2000, DATE '00.

[14]  Massoud Pedram,et al.  Standby and Active Leakage Current Control and Minimization in CMOS VLSI Circuits , 2005, IEICE Trans. Electron..

[15]  Sujit Dey,et al.  Design space exploration for optimizing on-chip communication architectures , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[16]  Luca Benini,et al.  Networks on Chips : A New SoC Paradigm , 2022 .

[17]  Srinivasan Murali,et al.  Bandwidth-constrained mapping of cores onto NoC architectures , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[18]  Timothy Mark Pinkston,et al.  A methodology for designing efficient on-chip interconnects on well-behaved communication patterns , 2003, The Ninth International Symposium on High-Performance Computer Architecture, 2003. HPCA-9 2003. Proceedings..

[19]  Radu Marculescu,et al.  Towards on-chip fault-tolerant communication , 2003, ASP-DAC '03.

[20]  Jörg Henkel,et al.  A design methodology for application-specific networks-on-chip , 2006, TECS.

[21]  Luca Benini,et al.  Analysis of error recovery schemes for networks on chips , 2005, IEEE Design & Test of Computers.

[22]  Alberto L. Sangiovanni-Vincentelli,et al.  Efficient synthesis of networks on chip , 2003, Proceedings 21st International Conference on Computer Design.

[23]  Radu Marculescu,et al.  Voltage-Frequency Island Partitioning for GALS-based Networks-on-Chip , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[24]  Radu Marculescu,et al.  Exploiting the Routing Flexibility for Energy/Performance Aware Mapping of Regular NoC Architectures , 2003, DATE.

[25]  Luca Benini,et al.  Networks on chips - technology and tools , 2006, The Morgan Kaufmann series in systems on silicon.