Dynamic instruction issue algorithm and a queue execution model toward the design of hybrid processor architecture

The evolution of microprocessor architecture depends upon the changing aspect of technology. As die density and speed increase, supported instructions set, compatibility and hardware innovations become increasingly important in defining architecture trade-offs. To satisfy the ever growing need for higher levels of computing power, computer architects need, then, to investigate techniques that continue improving the performance of microprocessors while considering both changing technology and applications. Conventional processors can achieve increased performance by issuing instructions Out-of-Order (OoO) from the original instruction stream. Implementing an OoO instruction issue scheme requires a powerful mechanism to prevent incorrectly executed instructions from updating registers values and to boost performance. In addition, performance degrades if dependencies, branches or traps among instructions appear. In this thesis, we first propose a new algorithm named Dynamic Fast Issue (DFI) mechanism to issue instructions in an out-of-order (OoO) scheme to multiple parallel functional units. The above system solves data dependencies, supports precise interrupt and branch prediction, which are the main problems associated with the dynamic scheduling of instructions in superscalar machines. Results are written only once, directly into the register file (RF). To ensure that results are written in order in their appropriate output registers, a record of instruction order and state is maintained by a status buffer (STB). To recover the processor state from an interrupt or a branch miss-prediction, a status buffer (STB) and a recovery list table (RLT) are implemented. Our performances evaluation results show that the DFI achieves a 12% average gain over the SUPER-Base conventional architecture for programs with varying level of IPC and high branch miss-predictions rates. Second, we propose an execution model's architecture that directly incorporates hardware Queue as its primarily data handling structure. We present a mathematical model for the QEM's instructions generation. We prove, then, that the Queue execution model’s instructions sequence can be correctly and easily generated from a parse tree and can be used to evaluate any arbitrary expression. In addition to the mathematical model, we give the novel aspects of the above execution model as well as the principle underlying the architecture. To experiment with our architecture innovation and to evaluate its efficiency, we build the architecture in software. A simulator, which determines the cycle count performance for some benchmark programs, was designed. The above Queue execution model and the DFI system are intended to be implemented in a so called Functional Assignment Register Microprocessor that embraces multi programming environments, combining the best futures of QEM and RISC models of computing. The novel aspects of the whole processor as well as the principle underlying the architecture are finally given.