Secure Processors Part II: Intel SGX Security Analysis and MIT Sanctum Architecture
暂无分享,去创建一个
[1] David Brumley,et al. Remote timing attacks are practical , 2003, Comput. Networks.
[2] David Grawrock. Dynamics of a trusted platform: a building block approach , 2009 .
[3] Xi Wang,et al. Linux kernel vulnerabilities: state-of-the-art defenses and open problems , 2011, APSys.
[4] Srinivas Devadas,et al. Intel SGX Explained , 2016, IACR Cryptol. ePrint Arch..
[5] Gorka Irazoqui Apecechea,et al. Seriously, get off my cloud! Cross-VM RSA Key Recovery in a Public Cloud , 2015, IACR Cryptol. ePrint Arch..
[6] Shay Gueron,et al. A Memory Encryption Engine Suitable for General Purpose Processors , 2016, IACR Cryptol. ePrint Arch..
[7] Michael Norrish,et al. seL4: formal verification of an OS kernel , 2009, SOSP '09.
[8] Marcelo Yuffe,et al. A fully integrated multi-CPU, GPU and memory controller 32nm processor , 2011, 2011 IEEE International Solid-State Circuits Conference.
[9] Srinivas Devadas,et al. A secure processor architecture for encrypted computation on untrusted programs , 2012, STC '12.
[10] C. Kozyrakis,et al. Scalable and Efficient Fine-grained Cache Partitioning with Vantage the Vantage Cache-partitioning Technique Enables Configurability and Quality-of-service Guarantees in Large-scale Chip Multiprocessors with Shared Caches. Caches Can Have Hundreds of Partitions with Sizes Specified at Cache Line Gra , 2011 .
[11] Xiaoyu Ruan. Platform Embedded Security Technology Revealed , 2014, Apress.
[12] Duflot,et al. Using CPU System Management Mode to Circumvent Operating System Security Functions , 2022 .
[13] Gorka Irazoqui Apecechea,et al. Fine Grain Cross-VM Attacks on Xen and VMware , 2014, 2014 IEEE Fourth International Conference on Big Data and Cloud Computing.
[14] Ittai Anati,et al. Innovative Technology for CPU Based Attestation and Sealing , 2013 .
[15] Yuval Yarom,et al. FLUSH+RELOAD: A High Resolution, Low Noise, L3 Cache Side-Channel Attack , 2014, USENIX Security Symposium.
[16] Neha Narula,et al. Native Client: A Sandbox for Portable, Untrusted x86 Native Code , 2009, IEEE Symposium on Security and Privacy.
[17] Srinivas Devadas,et al. Silicon physical random functions , 2002, CCS '02.
[18] Rafal Wojtczuk,et al. Attacking Intel TXT via SINIT code execution hijacking , 2011 .
[19] Jiangtao Li,et al. Enhanced Privacy ID from Bilinear Pairing for Hardware Authentication and Attestation , 2010, 2010 IEEE Second International Conference on Social Computing.
[20] G. Edward Suh,et al. Design and implementation of the AEGIS single-chip secure processor using physical random functions , 2005, 32nd International Symposium on Computer Architecture (ISCA'05).
[21] Gernot Heiser,et al. CATalyst: Defeating last-level cache side channel attacks in cloud computing , 2016, 2016 IEEE International Symposium on High Performance Computer Architecture (HPCA).
[22] Srinivas Devadas,et al. Security challenges and opportunities in adaptive and reconfigurable hardware , 2011, 2011 IEEE International Symposium on Hardware-Oriented Security and Trust.
[23] Richard E. Kessler,et al. Page placement algorithms for large real-indexed caches , 1992, TOCS.
[24] Billy Bob Brumley,et al. Remote Timing Attacks Are Still Practical , 2011, ESORICS.
[25] Larry Carter,et al. New Hash Functions and Their Use in Authentication and Set Equality , 1981, J. Comput. Syst. Sci..
[26] Nicolas Le Scouarnec,et al. Reverse Engineering Intel Last-Level Cache Complex Addressing Using Performance Counters , 2015, RAID.
[27] G. Edward Suh,et al. Physical Unclonable Functions for Device Authentication and Secret Key Generation , 2007, 2007 44th ACM/IEEE Design Automation Conference.
[28] Ruby B. Lee,et al. Random Fill Cache Architecture , 2014, 2014 47th Annual IEEE/ACM International Symposium on Microarchitecture.
[29] Yunsup Lee,et al. A 45nm 1.3GHz 16.7 double-precision GFLOPS/W RISC-V processor with vector accelerators , 2014, ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC).
[30] Christoforos E. Kozyrakis,et al. The ZCache: Decoupling Ways and Associativity , 2010, 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture.
[31] Brent Waters,et al. Cloaking Malware with the Trusted Platform Module , 2011, USENIX Security Symposium.
[32] Joseph Bonneau,et al. Cache-Collision Timing Attacks Against AES , 2006, CHES.
[33] Paul C. Kocher,et al. Timing Attacks on Implementations of Diffie-Hellman, RSA, DSS, and Other Systems , 1996, CRYPTO.
[34] Whitfield Diffie,et al. New Directions in Cryptography , 1976, IEEE Trans. Inf. Theory.
[35] Jean-Pierre Seifert,et al. Deconstructing new cache designs for thwarting software cache-based side channel attacks , 2008, CSAW '08.
[36] Larry Carter,et al. Universal Classes of Hash Functions , 1979, J. Comput. Syst. Sci..
[37] Krste Asanovic,et al. The RISC-V Instruction Set Manual Volume 2: Privileged Architecture Version 1.7 , 2015 .
[38] Zhao Zhang,et al. Gaining insights into multicore cache partitioning: Bridging the gap between simulation and real systems , 2008, 2008 IEEE 14th International Symposium on High Performance Computer Architecture.
[39] Carlos V. Rozas,et al. Innovative instructions and software model for isolated execution , 2013, HASP '13.
[40] Oded Goldreich,et al. Towards a theory of software protection and simulation by oblivious RAMs , 1987, STOC.
[41] Shay Gueron. Quick Verification of RSA Signatures , 2011, 2011 Eighth International Conference on Information Technology: New Generations.
[42] Gernot Heiser,et al. Last-Level Cache Side-Channel Attacks are Practical , 2015, 2015 IEEE Symposium on Security and Privacy.
[43] Srinivas Devadas,et al. Secure Processors Part I: Background, Taxonomy for Secure Enclaves and Intel SGX Architecture , 2017, Found. Trends Electron. Des. Autom..
[44] Ingrid Verbauwhede,et al. Low-Overhead Implementation of a Soft Decision Helper Data Algorithm for SRAM PUFs , 2009, CHES.
[45] Nael B. Abu-Ghazaleh,et al. Iso-X: A Flexible Architecture for Hardware-Managed Isolated Execution , 2014, 2014 47th Annual IEEE/ACM International Symposium on Microarchitecture.
[46] Gernot Heiser,et al. Mapping the Intel Last-Level Cache , 2015, IACR Cryptol. ePrint Arch..
[47] Angelos D. Keromytis,et al. The Spy in the Sandbox: Practical Cache Attacks in JavaScript and their Implications , 2015, CCS.
[48] Carl A. Gunter,et al. Leaky Cauldron on the Dark Land: Understanding Memory Side-Channel Hazards in SGX , 2017, CCS.
[49] Peter Davies,et al. The TLB slice-a low-cost high-speed address translation mechanism , 1990, [1990] Proceedings. The 17th Annual International Symposium on Computer Architecture.
[50] Nael B. Abu-Ghazaleh,et al. Non-monopolizable caches: Low-complexity mitigation of cache side channel attacks , 2012, TACO.
[51] Stefan M. Petters,et al. Making worst case execution time analysis for hard real-time tasks on state of the art processors feasible , 1999, Proceedings Sixth International Conference on Real-Time Computing Systems and Applications. RTCSA'99 (Cat. No.PR00306).
[52] Ling Ren,et al. Path ORAM , 2012, J. ACM.
[53] Chris Fallin,et al. Flipping bits in memory without accessing them: An experimental study of DRAM disturbance errors , 2014, 2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA).
[54] Stefan Mangard,et al. Reverse Engineering Intel DRAM Addressing and Exploitation , 2015, ArXiv.
[55] Ruby B. Lee,et al. New cache designs for thwarting software cache-based side channel attacks , 2007, ISCA '07.
[56] Marcus Peinado,et al. Controlled-Channel Attacks: Deterministic Side Channels for Untrusted Operating Systems , 2015, 2015 IEEE Symposium on Security and Privacy.
[57] Yunsup Lee,et al. The RISC-V Instruction Set Manual , 2014 .
[58] Cliff Changchun Zou,et al. SMM rootkit: a new breed of OS independent malware , 2013, Secur. Commun. Networks.
[59] Juan del Cuvillo,et al. Using innovative instructions to create trustworthy software solutions , 2013, HASP '13.
[60] G. Edward Suh,et al. AEGIS: architecture for tamper-evident and tamper-resistant processing , 2003 .
[61] Marcus Peinado,et al. Inferring Fine-grained Control Flow Inside SGX Enclaves with Branch Shadowing , 2016, USENIX Security Symposium.
[62] Hovav Shacham,et al. Hey, you, get off of my cloud: exploring information leakage in third-party compute clouds , 2009, CCS.