TSV Stress-Aware ATPG for 3D Stacked ICs

Thermo-mechanical stress due to TSV fabrication processes is a major concern in 3D integration. TSV stress not only degrades the mechanical reliability of 3D ICs but it also affects the electrical properties, such as electron and hole mobility, of the MOS devices surrounding TSVs. Variations in carrier mobility result in a change in the timing profile of the circuit, which has an impact on delay-fault testing. We show quantitatively using the SDQL metric that test quality is significantly reduced if the test patterns are generated with TSV stress-oblivious circuit models. We evaluate the impact on TSV stress on delay testing by considering layouts for several 3D logic-on-logic benchmarks. The test escape rate is higher for processes with lower yields. Our results also indicate that we can improve the test quality by using TSV-stress aware cell libraries in a conventional ATPG flow with commercial tools, with negligible impact on pattern count. We therefore conclude that any detrimental impact of TSV stress on pattern effectiveness and test quality can be overcome by using stress-aware models for test generation.

[1]  Mario H. Konijnenburg,et al.  A structured and scalable test access architecture for TSV-based 3D stacked ICs , 2010, 2010 28th VLSI Test Symposium (VTS).

[2]  Mark Mohammad Tehranipoor,et al.  Timing-based delay test for screening small delay defects , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[3]  Yervant Zorian,et al.  Testing 3D chips containing through-silicon vias , 2009, 2009 International Test Conference.

[4]  Sung Kyu Lim,et al.  Design method and test structure to characterize and repair TSV defect induced signal degradation in 3D system , 2010, 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[5]  Erik Jan Marinissen,et al.  DfT Architecture for 3D-SICs with Multiple Towers , 2011, 2011 Sixteenth IEEE European Test Symposium.

[6]  Kaustav Banerjee,et al.  Interconnect limits on gigascale integration (GSI) in the 21st century , 2001, Proc. IEEE.

[7]  Mario H. Konijnenburg,et al.  Automation of 3D-DfT Insertion , 2011, 2011 Asian Test Symposium.

[8]  Ding-Ming Kwai,et al.  On-chip testing of blind and open-sleeve TSVs for 3D IC before bonding , 2010, 2010 28th VLSI Test Symposium (VTS).

[9]  Toshiyuki Maeda,et al.  Invisible delay quality - SDQM model lights up what could not be seen , 2005, IEEE International Conference on Test, 2005..

[10]  Paul Enquist,et al.  Low Cost of Ownership scalable copper Direct Bond Interconnect 3D IC technology for three dimensional integrated circuit applications , 2009, 2009 IEEE International Conference on 3D System Integration.

[11]  R. Ramani,et al.  CMOS stress sensors on [100] silicon , 2000, IEEE Journal of Solid-State Circuits.

[12]  Kaustav Banerjee,et al.  3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration , 2001, Proc. IEEE.

[13]  Mark Mohammad Tehranipoor,et al.  Test-Pattern Selection for Screening Small-Delay Defects in Very-Deep Submicrometer Integrated Circuits , 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[14]  Erik Jan Marinissen,et al.  Testing TSV-based three-dimensional stacked ICs , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

[15]  Jae-Seok Yang,et al.  TSV stress aware timing analysis with applications to 3D-IC layout optimization , 2010, Design Automation Conference.

[16]  W. Dehaene,et al.  Electrical Modeling and Characterization of Through Silicon via for Three-Dimensional ICs , 2010, IEEE Transactions on Electron Devices.

[17]  Hsien-Hsin S. Lee,et al.  Test Challenges for 3D Integrated Circuits , 2009, IEEE Design & Test of Computers.

[18]  Edward J. McCluskey,et al.  Delay defect screening using process monitor structures , 2004, 22nd IEEE VLSI Test Symposium, 2004. Proceedings..

[19]  Paul S. Ho,et al.  Thermomechanical reliability of through-silicon vias in 3D interconnects , 2011, 2011 International Reliability Physics Symposium.

[20]  Thuy Dao,et al.  Through Silicon Via stress characterization , 2009, 2009 IEEE International Conference on IC Design and Technology.

[21]  Erik Jan Marinissen,et al.  Evaluation of TSV and micro-bump probing for wide I/O testing , 2011, 2011 IEEE International Test Conference.

[22]  Chen Wang,et al.  Timing-Aware ATPG for High Quality At-speed Testing of Small Delay Defects , 2006, 2006 15th Asian Test Symposium.

[23]  Sung Kyu Lim,et al.  A study of Through-Silicon-Via impact on the 3D stacked IC layout , 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.

[24]  Krishnendu Chakrabarty,et al.  Pre-bond probing of TSVs in 3D stacked ICs , 2011, 2011 IEEE International Test Conference.