Lane departure warning system based on FPGA

This paper designs a lane departure warning system which takes FPGA as process core,in order to solve cost and performance of the traditional machine vision processing system.Then it researches on the lane line extracting and lane departure warning algorithm and realizes the parallel algorithm through RTL level design,and sets up the SOPC system which integrates the head up display system.The design can reduce the extra processor,and supply more secure driving experience.The design can cost less than the traditional visual processing DSP platform,and system can meet the real-time whose image processing rate can reach 1157 frames per second.