A Survey of Coarse-Grain Reconfigurable Architectures and Cad Tools

[1]  Shahram Shirani,et al.  Run-Time Reconfigurable Systems for Digital Signal Processing Applications: A Survey , 2005, J. VLSI Signal Process..

[2]  Seth Copen Goldstein,et al.  PipeRench: A Reconfigurable Architecture and Compiler , 2000, Computer.

[3]  Gerard J. M. Smit,et al.  Mapping of DSP algorithms on the MONTIUM architecture , 2003, Proceedings International Parallel and Distributed Processing Symposium.

[4]  Takashi Miyamori,et al.  REMARC: Reconfigurable Multimedia Array Coprocessor (Abstract). , 1998 .

[5]  Paolo Ienne,et al.  Automatic application-specific instruction-set extensions under microarchitectural constraints , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[6]  李幼升,et al.  Ph , 1989 .

[7]  Jason Cong,et al.  Application-specific instruction generation for configurable processor architectures , 2004, FPGA '04.

[8]  Stamatis Vassiliadis,et al.  Field-Programmable Custom Computing Machines - A Taxonomy - , 2002, FPL.

[9]  Seth Copen Goldstein,et al.  PipeRench: a co/processor for streaming multimedia acceleration , 1999, ISCA.

[10]  Kiyoung Choi,et al.  Compilation approach for coarse-grained reconfigurable architectures , 2003, IEEE Design & Test of Computers.

[11]  Majid Sarrafzadeh,et al.  A quick safari through the reconfiguration jungle , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[12]  Rudy Lauwereins,et al.  DRESC: a retargetable compiler for coarse-grained reconfigurable architectures , 2002, 2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings..

[13]  Luciano Lavagno,et al.  Software development for high-performance, reconfigurable, embedded multimedia systems , 2005, IEEE Design & Test of Computers.

[14]  Scott Hauck,et al.  Architecture generation of customized reconfigurable hardware , 2003 .

[15]  Scott Hauck,et al.  Flexibility measurement of domain-specific reconfigurable hardware , 2004, FPGA '04.

[16]  Luciano Lavagno,et al.  Hardware/software design space exploration for a reconfigurable processor , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[17]  Carl Ebeling,et al.  Architecture design of reconfigurable pipelined datapaths , 1999, Proceedings 20th Anniversary Conference on Advanced Research in VLSI.

[18]  George Theodoridis,et al.  A RISC architecture extended by an efficient tightly coupled reconfigurable unit , 2006 .

[19]  D. Bhatia,et al.  Reconfigurable computing , 1997, Proceedings Tenth International Conference on VLSI Design.

[20]  Rudy Lauwereins,et al.  Design methodology for a tightly coupled VLIW/reconfigurable matrix architecture: a case study , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[21]  Rudy Lauwereins,et al.  Architecture exploration for a reconfigurable architecture template , 2005, IEEE Design & Test of Computers.

[22]  Robert A. Scholtz,et al.  Performance Analysis of , 1998 .

[23]  J. P. Grossman,et al.  Characterization and parameterized generation of synthetic combinational benchmark circuits , 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[24]  Rajesh Gupta,et al.  Network topology exploration of mesh-based coarse-grain reconfigurable architectures , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[25]  Reiner W. Hartenstein.  Coarse grain reconfigurable architecture (embedded tutorial) , 2001, ASP-DAC '01.

[26]  Jan M. Rabaey,et al.  Interconnect architecture exploration for low-energy reconfigurable single-chip DSPs , 1999, Proceedings. IEEE Computer Society Workshop on VLSI '99. System Design: Towards System-on-a-Chip Paradigm.

[27]  Scott Hauck,et al.  Totem: Custom Reconfigurable Array Generation , 2001, The 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'01).

[28]  Scott Hauck,et al.  Flexible Routing Architecture Generation for Domain-Specific Reconfigurable Subsystems , 2002, FPL.

[29]  Miodrag Potkonjak,et al.  Performance optimization using template mapping for datapath-intensive high-level synthesis , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[30]  Sharad Malik,et al.  Exploiting operation level parallelism through dynamically reconfigurable datapaths , 2002, DAC '02.

[31]  Jan M. Rabaey,et al.  Ultra-low-power domain-specific multimedia processors , 1996, VLSI Signal Processing, IX.

[32]  Wayne Wei-Ming Dai,et al.  A Method for Generation Random Circuits and Its Application to Routability Measurement , 1996, Fourth International ACM Symposium on Field-Programmable Gate Arrays.

[33]  Michalis D. Galanis,et al.  A compiler method for memory-conscious mapping of applications on coarse-grained reconfigurable architectures , 2005, 19th IEEE International Parallel and Distributed Processing Symposium.

[34]  Steven J. E. Wilton,et al.  Structural analysis and generation of synthetic digital circuits with memory , 2001, IEEE Trans. Very Large Scale Integr. Syst..

[35]  Sharad Malik,et al.  The design of dynamically reconfigurable datapath coprocessors , 2004, TECS.

[36]  Fadi J. Kurdahi,et al.  Automatic compilation to a coarse-grained reconfigurable system-opn-chip , 2003, TECS.

[37]  Patrice Quinton,et al.  Systolic algorithms and architectures , 1987 .

[38]  Majid Sarrafzadeh,et al.  Instruction generation for hybrid reconfigurable systems , 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).

[39]  Rudy Lauwereins,et al.  ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix , 2003, FPL.

[40]  D. Verkest,et al.  Exploiting loop-level parallelism on coarse-grained reconfigurable architectures using modulo scheduling , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[41]  S. Cadambi,et al.  CPR: a configuration profiling tool , 1999, Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines (Cat. No.PR00375).

[42]  Markus Weinhardt,et al.  PACT XPP—A Self-Reconfigurable Data Processing Architecture , 2004, The Journal of Supercomputing.

[43]  George Theodoridis,et al.  Exploring opportunities to improve the performance of a reconfigurable instruction set processor , 2007 .

[44]  Sharad Malik,et al.  Managing dynamic reconfiguration overhead in systems-on-a-chip design using reconfigurable datapaths and optimized interconnection networks , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

[45]  Fadi J. Kurdahi,et al.  MorphoSys: An Integrated Reconfigurable System for Data-Parallel and Computation-Intensive Applications , 2000, IEEE Trans. Computers.

[46]  John Wawrzynek,et al.  Reconfigurable computing: what, why, and implications for design automation , 1999, DAC '99.

[47]  George Varghese,et al.  Design Methodology of a Low-Energy Reconfigurable Single-Chip DSP System , 2001, J. VLSI Signal Process..

[48]  Jonathan Rose,et al.  Automatic generation of synthetic sequential benchmark circuits , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[49]  Carl Ebeling,et al.  Placement and routing tools for the Triptych FPGA , 1995, IEEE Trans. Very Large Scale Integr. Syst..

[50]  F. Gregoretti,et al.  Implementation of a UMTS turbo-decoder on a dynamically reconfigurable platform , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[51]  Rudy Lauwereins,et al.  Reconfigurable Instruction Set Processors from a Hardware/Software Perspective , 2002, IEEE Trans. Software Eng..

[52]  Reiner W. Hartenstein,et al.  A decade of reconfigurable computing: a visionary retrospective , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

[53]  Luciano Lavagno,et al.  A software development tool chain for a reconfigurable processor , 2001, CASES '01.

[54]  Carl Ebeling,et al.  Mapping applications to the RaPiD configurable architecture , 1997, Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186).

[55]  Markus Weinhardt,et al.  XPP-VC: A C Compiler with Temporal Partitioning for the PACT-XPP Architecture , 2002, FPL.

[56]  Kunle Olukotun,et al.  REMARC (abstract): reconfigurable multimedia array coprocessor , 1998, FPGA '98.

[57]  Gerard J. M. Smit,et al.  A Flexible and Energy-Efficient Coarse-Grained Reconfigurable Architecture for Mobile Systems , 2003, The Journal of Supercomputing.

[58]  Reiner W. Hartenstein.  Coarse grain reconfigurable architectures , 2001, Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455).

[59]  Scott Hauck,et al.  Reconfigurable computing: a survey of systems and software , 2002, CSUR.

[60]  A. Lodi,et al.  A VLIW processor with reconfigurable instruction set for embedded applications , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[61]  Kunle Olukotun,et al.  REMARC : Reconfigurable Multimedia Array Coprocessor , 1999 .

[62]  Seth Copen Goldstein,et al.  Managing pipeline-reconfigurable FPGAs , 1998, FPGA '98.