论文信息 - A reconfigurable VLSI learning array

A reconfigurable VLSI learning array

We present a reconfigurable array for low-power feedforward neural networks in analog VLSI. This architecture implements a flexible computational model with coarse-grained reconfigurability, and features high computational density for a broad range of applications. Our prototype of the array, fabricated in a 0.35/spl mu/m process, consumes 0.25mm/sup 2/ of area and dissipates 150/spl mu/W of power on a 5V supply. In this paper, we discuss the circuits and architecture of our system, as well as experimental results.

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