Characterization of tunneling current in ultra-thin gate oxide

Abstract Experimental measurements and physical modeling of the tunneling current through ultra-thin gate oxides (1–6 nm) are presented for a large variety of experimental conditions including injection of electrons and holes from both accumulation and inversion layers and different cathode/anode polarities. By comparing experiments and simulations, the following issues are addressed: (i) importance of different components of the tunneling current; (ii) impact of quantization effects; (iii) sensitivity to the device structural parameters (doping levels, oxide thickness, etc.); (iv) impact of different stress conditions during aging experiments. The results of this study indicate the importance of quantum mechanical modeling and the presence of many tunneling mechanisms in ultra-thin oxide MOS devices, and that I–V measurements may be used for oxide characterization at thickness levels where other techniques (C–V) become inaccurate.

[1]  R. Fowler,et al.  Electron Emission in Intense Electric Fields , 1928 .

[2]  Jordi Suñé,et al.  Self-consistent solution of the Poisson and Schrödinger equations in accumulated semiconductor-insulator interfaces , 1991 .

[3]  E. Sangiorgi,et al.  Low voltage tunneling in ultra-thin oxides: a monitor for interface states and degradation , 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

[4]  A. Ghetti,et al.  Progress toward 10 nm CMOS devices , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

[5]  M. Lenzlinger,et al.  Fowler‐Nordheim Tunneling into Thermally Grown SiO2 , 1969 .

[6]  W. Lui,et al.  Exact solution of the Schrodinger equation across an arbitrary one‐dimensional piecewise‐linear potential barrier , 1986 .

[7]  P.J. Silverman,et al.  Explanation of stress-induced damage in thin oxides , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

[8]  A. Agarwal,et al.  Low leakage, ultra-thin gate oxides for extremely high performance sub-100 nm nMOSFETs , 1997, International Electron Devices Meeting. IEDM Technical Digest.

[9]  Z. Weinberg,et al.  On tunneling in metal‐oxide‐silicon structures , 1982 .

[10]  Chenming Hu,et al.  Hot-Electron-Induced MOSFET Degradation - Model, Monitor, and Improvement , 1985, IEEE Journal of Solid-State Circuits.

[11]  Y. Taur,et al.  Quantum-mechanical modeling of electron tunneling current from the inversion layer of ultra-thin-oxide nMOSFET's , 1997, IEEE Electron Device Letters.

[12]  A. Pacelli,et al.  Self-consistent solution of the Schrodinger equation in semiconductor devices by implicit iteration , 1997 .

[13]  S. Tiwari,et al.  Self‐consistent modeling of accumulation layers and tunneling currents through very thin oxides , 1996 .

[14]  F. Stern,et al.  Properties of Semiconductor Surface Inversion Layers in the Electric Quantum Limit , 1967 .

[15]  Chenming Hu,et al.  Hot-electron-induced MOSFET degradation—Model, monitor, and improvement , 1985, IEEE Transactions on Electron Devices.

[16]  A. Ghetti,et al.  Modeling and Simulation of Tunneling Current in MOS Devices Including Quantum Mechanical Effects , 2000 .

[17]  C. Liu,et al.  Circuit requirement and integration challenges of thin gate dielectrics for ultra small MOSFETs , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

[18]  N. Lifshitz,et al.  Dependence of the work-function difference between the polysilicon gate and silicon substrate on the doping level in polysilicon , 1985, IEEE Transactions on Electron Devices.

[19]  Yuan Taur,et al.  CMOS scaling into the 21st century: 0.1 µm and beyond , 1995, IBM J. Res. Dev..

[20]  P. Silverman,et al.  Ultra-thin gate oxides and ultra-shallow junctions for high performance, sub-100 nm pMOSFETs , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

[21]  H. Iwai,et al.  1.5 nm direct-tunneling gate oxide Si MOSFET's , 1996 .

[22]  I. C. Kizilyalli,et al.  Three-dimensional characterization of bipolar transistors in a submicron BiCMOS technology using integrated process and device simulation , 1992, 1992 International Technical Digest on Electron Devices Meeting.

[23]  James P. Shiely,et al.  The role of substrate carrier generation in determining the electric field in the oxide of MOS capacitors biased in the Fowler-Norheim tunneling regime , 1997 .

[24]  T. Ma,et al.  Polarity dependent gate tunneling currents in dual-gate CMOSFETs , 1998 .

[25]  G. Klimeck,et al.  Physical oxide thickness extraction and verification using quantum mechanical simulation , 1997, International Electron Devices Meeting. IEDM Technical Digest.

[26]  G. Alers,et al.  Intrinsic and stress-induced traps in the direct tunneling current of 2.3-3.8 nm oxides and unified characterization methodologies of sub-3 nm oxides , 1997, International Electron Devices Meeting. IEDM Technical Digest.

[27]  H. Vaidya,et al.  Self-consistent simulation of quantization effects and tunneling current in ultra-thin gate oxide MOS devices , 1999, 1999 International Conference on Simulation of Semiconductor Processes and Devices. SISPAD'99 (IEEE Cat. No.99TH8387).