A multi-level ladder converter supporting vertically-stacked digital voltage domains
暂无分享,去创建一个
[1] Peng Xu,et al. Investigation of candidate VRM topologies for future microprocessors , 2000 .
[2] Milan M. Jovanovic,et al. Design considerations for 12-V/1.5-V, 50-A voltage regulator modules , 2000, APEC 2000. Fifteenth Annual IEEE Applied Power Electronics Conference and Exposition (Cat. No.00CH37058).
[3] Philip T. Krein,et al. Differential Power Processing for DC Systems , 2013, IEEE Transactions on Power Electronics.
[4] Seth R. Sanders,et al. A 2.4GHz, 20dBm class-D PA with single-bit digital polar modulation in 90nm CMOS , 2008, 2008 IEEE Custom Integrated Circuits Conference.
[5] Anantha P. Chandrakasan,et al. Minimizing power consumption in digital CMOS circuits , 1995, Proc. IEEE.
[6] Henk Jan Bergveld,et al. Module-Level DC/DC Conversion for Photovoltaic Systems: The Delta-Conversion Concept , 2013, IEEE Transactions on Power Electronics.
[7] Geoffrey R. Walker,et al. Photovoltaic DC-DC module integrated converter for novel cascaded and bypass grid connection topologies - design and optimisation , 2006 .
[8] Michael D. Seeman,et al. A 32nm fully integrated reconfigurable switched-capacitor DC-DC converter delivering 0.55W/mm2 at 81% efficiency , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).
[9] Seth R. Sanders,et al. Architecture and IC implementation of a digital VRM controller , 2003 .
[10] Brian P. Ginsburg,et al. The mixed signal optimum energy point: Voltage and parallelism , 2008, 2008 45th ACM/IEEE Design Automation Conference.
[11] A.V. Peterchev,et al. Design of ceramic-capacitor VRM's with estimated load current feedforward , 2004, 2004 IEEE 35th Annual Power Electronics Specialists Conference (IEEE Cat. No.04CH37551).
[12] S. Rajapandian,et al. High-voltage power delivery through charge recycling , 2006, IEEE Journal of Solid-State Circuits.
[13] P. T. Krein,et al. Comparative analysis of differential power conversion architectures and controls for solar photovoltaics , 2012, 2012 IEEE 13th Workshop on Control and Modeling for Power Electronics (COMPEL).
[14] P. Hazucha,et al. A 100MHz Eight-Phase Buck Converter Delivering 12A in 25mm2 Using Air-Core Inductors , 2007, APEC 07 - Twenty-Second Annual IEEE Applied Power Electronics Conference and Exposition.
[15] Elad Alon,et al. Integrated Regulation for Energy-Efficient Digital Circuits , 2008, IEEE J. Solid State Circuits.
[16] S. Rajapandian,et al. Implicit DC-DC downconversion through charge-recycling , 2005, IEEE Journal of Solid-State Circuits.
[17] K. Kesarwani,et al. A comparative theoretical analysis of distributed ladder converters for sub-module PV energy optimization , 2012, 2012 IEEE 13th Workshop on Control and Modeling for Power Electronics (COMPEL).
[18] O. Trescases,et al. DC-DC converter for high granularity, sub-string MPPT in photovoltaic applications using a virtual-parallel connection , 2012, 2012 Twenty-Seventh Annual IEEE Applied Power Electronics Conference and Exposition (APEC).
[19] Charles R. Sullivan,et al. Coupled-inductor design optimization for fast-response low-voltage DC-DC converters , 2002, APEC. Seventeenth Annual IEEE Applied Power Electronics Conference and Exposition (Cat. No.02CH37335).
[20] S. Rajapandian,et al. A Linear Regulator with Fast Digital Control for Biasing Integrated DC-DC Converters , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.
[21] B. Bakkaloglu,et al. A Multi-Stage Interleaved Synchronous Buck Converter with Integrated Output Filter in a 0.18/spl mu/ SiGe process , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.
[22] Dragan Maksimovic,et al. Switched-capacitor DC-DC converters for low-power on-chip applications , 1999, 30th Annual IEEE Power Electronics Specialists Conference. Record. (Cat. No.99CH36321).
[23] Michael D. Seeman,et al. A high-voltage CMOS IC and embedded system for distributed photovoltaic energy optimization with over 99% effective conversion efficiency and insertion loss below 0.1% , 2012, 2012 IEEE International Solid-State Circuits Conference.