Bit-Slice Butterfly Processing Units for 64-Point RSFQ FFT Processors

In this article, 8-bit bit-slice butterfly processing units (BPUs) are proposed for 64-point rapid single-flux-quantum (RSFQ) fast Fourier transform processors. The BPUs are based on radix-2, mixed-radix, and split-radix algorithms, respectively. Unlike the previously developed bit-serial RSFQ BPUs, the proposed bit-slice BPUs continuously process 64-point data divided into eight slices of eight points each in order to reduce the hardware cost. The BPUs use synchronous concurrent-flow clocking and they can be extended to any <inline-formula><tex-math notation="LaTeX">$n^2$</tex-math></inline-formula>-point processing.

[1]  N. Takagi,et al.  4-bit Bit-Slice Arithmetic Logic Unit for 32-bit RSFQ Microprocessors , 2016, IEEE Transactions on Applied Superconductivity.

[2]  C. Burrus,et al.  An in-place, in-order prime factor FFT algorithm , 1981 .

[3]  Y. Yamanashi,et al.  Design and Implementation of a Pipelined Bit-Serial SFQ Microprocessor, ${\rm CORE}1\beta$ , 2007, IEEE Transactions on Applied Superconductivity.

[4]  J. Tukey,et al.  An algorithm for the machine calculation of complex Fourier series , 1965 .

[5]  Franz Franchetti,et al.  Computer Generation of Hardware for Linear Digital Signal Processing Transforms , 2012, TODE.

[6]  P. Duhamel,et al.  `Split radix' FFT algorithm , 1984 .

[7]  Yuki Yamanashi,et al.  50 GHz Demonstration of an Integer-Type Butterfly Processing Circuit for an FFT Processor Using the 10 kA/cm2 Nb Process , 2015, IEICE Trans. Electron..

[8]  Kazuyoshi Takagi,et al.  Nb 9-Layer Fabrication Process for Superconducting Large-Scale SFQ Circuits and Its Process Evaluation , 2014, IEICE Trans. Electron..

[9]  Guang-Ming Tang,et al.  Logic Design of a 16-bit Bit-Slice Arithmetic Logic Unit for 32-/64-bit RSFQ Microprocessors , 2018, IEEE Transactions on Applied Superconductivity.

[10]  O. Mukhanov,et al.  Implementation of a FFT radix 2 butterfly using serial RSFQ multiplier-adders , 1995, IEEE Transactions on Applied Superconductivity.

[11]  Kazuyoshi Takagi,et al.  Design and Demonstration of an 8-bit Bit-Serial RSFQ Microprocessor: CORE e4 , 2016, IEEE Transactions on Applied Superconductivity.

[12]  Kazuyoshi Takagi,et al.  RSFQ 4-bit Bit-Slice Integer Multiplier , 2016, IEICE Trans. Electron..

[13]  Y. Yamanashi,et al.  High-Speed Operation of an SFQ Butterfly Processing Circuit for FFT Processors Using the 10 kA/cm2 Nb Process , 2015, IEEE Transactions on Applied Superconductivity.

[14]  Yuki Yamanashi,et al.  100 GHz Demonstrations Based on the Single-Flux-Quantum Cell Library for the 10 kA/cm2 Nb Multi-Layer Process , 2010, IEICE Trans. Electron..

[15]  Guang-Ming Tang,et al.  32-Bit 4 × 4 Bit-Slice RSFQ Matrix Multiplier , 2018, IEEE Transactions on Applied Superconductivity.

[16]  V. Semenov,et al.  RSFQ logic/memory family: a new Josephson-junction technology for sub-terahertz-clock-frequency digital systems , 1991, IEEE Transactions on Applied Superconductivity.

[17]  N. Takagi,et al.  32 × 32-Bit 4-Bit Bit-Slice Integer Multiplier for RSFQ Microprocessors , 2017, IEEE Transactions on Applied Superconductivity.