빠른 스위칭 시간과 저 위상잡음 특성을 가지는 PHS용 주파수 합성기의 설계

This paper presents a fast switching CMOS frequency synthesizer with a new coarse tuning method for PHS applications. To achieve the fast lock-time and the low phase noise performance, an efficient bandwidth control scheme is proposed. Charge pump up/down current mismatches are compensated with the current mismatch compensation block. Also, the proposed coarse tuning method selects the optimal tuning capacitances of the LC-VCO to optimize the phase noise and the lock-time. The measured lock-time is about 20㎲. This chip is fabricated with 0.25㎛ CMOS technology, and the die area is 0.7㎜ x 2.1㎜. The power consumption is 54mW at 2.7V supply voltage.