Circuit design techniques for multi-bit third-order oversampling converter

Abstract Third-order sigma-delta ADCs and DACs with 3-bit internal quantization have been implemented with 1·2 μm CMOS technology, employing the individual averaging technique to eliminate the harmonic distortion due to element mismatch. The projected result of the ΣΔ ADC has a dynamic range of 102 dB from the simulation. The extracted circuit from the layout runs at a clock rate of 5 MHz. In addition, a prototype third order ΣΔ DAC implemented using discrete components has been tested. Testing results show that the harmonic distortion is reduced by 16 dB by using the individual averaging technique, compared with a conventional D/A structure.