Energy Efficient Write Verify and Retry Scheme for MTJ Based Flip-Flop and Application

A non-volatile flip-flop (NVFF) introducing MTJ has many strong points in high endurance and read/write performance, and hence is very attractive as a component to be used for power gating of sequential circuits. However, large write-energy to MTJ becomes a big obstacle in achieving low energy dissipation. This paper proposes a NVFF circuit enabling to verify the success of a store operation to MTJ and retry it by prolonging the store time. We designed a NVFF circuit with this feature and applied it to 20,000 flip-flops in a dynamically reconfigurable processor (DRP). We conducted simulations considering write time variations caused by various factors such as process variations and thermal fluctuations. The results demonstrated that the proposed approach reduces store energy by 35-36% at four image-processing applications and the break-even time (BET) for non-volatile power gating is 2.0-2.9us at the 0.004% write error rate, at which no failures occur for the total number of NVFFs in the DRP.

[1]  Lionel Torres,et al.  Trends on the application of emerging nonvolatile memory to processors and programmable devices , 2013, 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013).

[2]  Daisuke Suzuki,et al.  Nonvolatile logic-in-memory array processor in 90nm MTJ/MOS achieving 75% leakage reduction using cycle-based power gating , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[3]  Hiroshi Nakamura,et al.  Cool Mega-Arrays: Ultralow-Power Reconfigurable Accelerator Chips , 2011, IEEE Micro.

[4]  Farshad Moradi,et al.  STT-RAM Energy Reduction Using Self-Referenced Differential Write Termination Technique , 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[5]  Yusuke Shuto,et al.  Nonvolatile delay flip-flop using spin-transistor architecture with spin transfer torque MTJs for power-gating systems , 2011 .

[6]  Weisheng Zhao,et al.  Electrical Modeling of Stochastic Spin Transfer Torque Writing in Magnetic Tunnel Junctions for Memory and Logic Applications , 2013, IEEE Transactions on Magnetics.

[7]  Seong-Ook Jung,et al.  High-performance low-power magnetic tunnel junction based non-volatile flip-flop , 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).

[8]  Pradip Bose,et al.  Microarchitectural techniques for power gating of execution units , 2004, Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758).

[9]  Jun Yang,et al.  Energy reduction for STT-RAM using early write termination , 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.

[10]  Massimo Alioto,et al.  A Variation-Aware Timing Modeling Approach for Write Operation in Hybrid CMOS/STT-MTJ Circuits , 2018, IEEE Transactions on Circuits and Systems I: Regular Papers.

[11]  Jacques-Olivier Klein,et al.  Analytical Macrospin Modeling of the Stochastic Switching Time of Spin-Transfer Torque Devices , 2015, IEEE Transactions on Electron Devices.

[12]  Wenqing Wu,et al.  Probabilistic design methodology to improve run-time stability and performance of STT-RAM caches , 2012, 2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[13]  Hiroshi Nakajima,et al.  A 6.14µA normally-off ECG-SoC with noise tolerant heart rate extractor for wearable healthcare systems , 2014, 2014 IEEE Biomedical Circuits and Systems Conference (BioCAS) Proceedings.

[14]  Nadine Eberhardt,et al.  Computer Organization And Design 2nd Edition , 2016 .

[15]  Kimiyoshi Usami,et al.  Nonvolatile power gating with MTJ based nonvolatile flip-flops for a microprocessor , 2017, 2017 IEEE 6th Non-Volatile Memory Systems and Applications Symposium (NVMSA).

[16]  Weisheng Zhao,et al.  Spin-MTJ based Non-volatile Flip-Flop , 2007, 2007 7th IEEE Conference on Nanotechnology (IEEE NANO).

[17]  Jaeyoung Park,et al.  Variable-energy write STT-RAM architecture with bit-wise write-completion monitoring , 2013, International Symposium on Low Power Electronics and Design (ISLPED).

[18]  Jacques-Olivier Klein,et al.  Ultra Low Power Magnetic Flip-Flop Based on Checkpointing/Power Gating and Self-Enable Mechanisms , 2014, IEEE Transactions on Circuits and Systems I: Regular Papers.