A New Recursive Multibit Recoding Algorithm for High-Speed and Low-Power Multiplier

r adapted technique for a multi-precision multiplication is presented. I. BACKGROUND AND MOTIVATION N multiplication-intensive applications, as in digital signal processing or process control, multiply-time is a critical factor that limits the whole system performance. When these types of applications are embedded, energy consumption per multiply operation becomes an additional critical issue. Furthermore, in high-precision or large-operand-size applications such as in cryptography, the need for a scalable serial/parallel multiplier is essential as the multiplier size grows quadratically O(n 2) with operand size n. Consequently, high-speed, low-power, and highly-scalable architecture are the three major requirements for today's general purpose multiplier [1]. The continuous refinement of the mostly-used design paradigm based on modified Booth algorithm [2] combined to a reduction tree (carry-save-adder array , Dadda[3], HPM[4]) has reached saturation. In [5] and [6] only slight improvements are achieved. Both proposals reduce the partial product number from n/2+1 to n/2 using different circuit optimization techniques of the critical path. Theoretically, only the signed multibit recoding multiplication algorithm [7] is capable of a drastic reduction (n/r) of the partial product number, given that r+1 is the number of bits of the multiplier that are simultaneously treated (1≤r≤n). Unfortunately, this algorithm requires the pre-computation of a number of odd multiples of the multiplicand (until (2 r-1-1).X) that scales linearly with r. The large number of odd multiples not only requires a considerable amount of multiplexers to perform the necessary complex recoding into PPG, but dramatically increases the routing density as well. Therefore, a reverse effect occurs that offsets speed and power benefits of the compression factor (n/r). This is the main reason why the multibit recoding algorithm was abandoned. In practice, designs do not exceed r=3 (radix 8). The current trend [8][9] relies upon advanced arithmetic to determine minimal numeric bases that are representatives of the digits resulting from larger multibit recoding. The objective is to eliminate information redundancy inside r+1 bit-length slices for a more compact PPG. This is achievable as long as no or just very few odd multiples are required. In [8], Seidel et al. have introduced a secondary recoding of digits issued from an initial multibit recoding for 5≤r≤16. The recoding scheme is based on balanced complete residue system. Though it significantly reduces the number of partial products (n/r for 5≤r≤ 16), it requires some odd multiples for r≥8. While in [9], Dimitrov et al. have proposed a new recoding scheme …