Design and Implementation of High Performance MAC Unit
暂无分享,去创建一个
[1] Kavita Khare,et al. Comparison of pipelined IEEE-754 standard floating point multiplier with unpipelined multiplier , 2006 .
[2] Vojin G. Oklobdzija,et al. High-Speed VLSI Arithmetic Units: Adders and Multipliers , 1999 .
[3] S. Y. Kulkarni,et al. Design and VLSI Implementation of Pipelined Multiply Accumulate Unit , 2009, 2009 Second International Conference on Emerging Trends in Engineering & Technology.
[4] M. Mohanapriya,et al. Area, Delay And Power Comparison Of Adder Topologies , 2012, VLSIC 2012.
[5] Earl E. Swartzlander,et al. A comparison of Dadda and Wallace multiplier delays , 2003, SPIE Optics + Photonics.
[6] A. Kanhe,et al. Design and implementation of floating point multiplier based on Vedic Multiplication Technique , 2012, 2012 International Conference on Communication, Information & Computing Technology (ICCICT).
[7] Aniruddha Kanhe,et al. DESIGN AND IMPLEMENT ATION OF LOW POWER MUL TIPLIER USING VEDIC MULTIPLICATION TECHNIQUE , 2012 .
[8] Dong-Wook Kim,et al. A New VLSI Architecture of Parallel Multiplier–Accumulator Based on Radix-2 Modified Booth Algorithm , 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[9] James Demmel,et al. IEEE Standard for Floating-Point Arithmetic , 2008 .
[10] Christopher S. Wallace,et al. A Suggestion for a Fast Multiplier , 1964, IEEE Trans. Electron. Comput..
[11] Paolo Montuschi,et al. Reducing the Computation Time in (Short Bit-Width) Two's Complement Multipliers , 2011, IEEE Transactions on Computers.
[12] B. P. Patil,et al. Performance Evaluation of Squaring Operation by Vedic Mathematics , 2011 .