Soft-error-rate improvement in advanced BiCMOS SRAMs

An improvement in soft-error-rate (SER) achieved by implementing a triple-well structure in a BiCMOS process is discussed. For 4-Mb SRAMs fabricated in a BiCMOS process, an optimized triple-well process improves the accelerated SER (ASER) by over two orders of magnitude without compromising device performance. Diode charge collection and ASER measurements show excellent correlation across several BiCMOS and CMOS processes.<<ETX>>

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