An Implementation of Pipelined Radix-4 FFT Architecture on FPGAs

16-point pipelined FFT architecture is presented. The architecture is based on the radix-4 algorithm. By exploiting the regularity of the algorithm, butterfly operation and multiplier modules were designed. The architecture adopts four butterflies, and the pipeline stage is optimized to balance the processing speed and the area. It was modeled by VHDL, and synthesized in FPGA. By adopting this architecture, the data throughput could be 2M/s. It is extensible for high point FFT.

[1]  Krzysztof Sapiecha,et al.  Modular Architecture for High Performance Implementation of FFT Algorithm , 1986, ISCA.

[2]  R. Ravi,et al.  Optimal Circuits for Parallel Multipliers , 1998, IEEE Trans. Computers.

[3]  E. V. Jones,et al.  A pipelined FFT processor for word-sequential data , 1989, IEEE Trans. Acoust. Speech Signal Process..

[4]  Shousheng He,et al.  Design and implementation of a 1024-point pipeline FFT processor , 1998, Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143).

[5]  Jaeseok Kim,et al.  Low complexity multi-point 4-channel FFT processor for IEEE 802.11n MIMO-OFDM WLAN system , 2012, 2012 International Conference on Green and Ubiquitous Technology.

[6]  W. B. Mikhael,et al.  Fast Fourier Transform for high speed OFDM wireless multimedia system , 2001, Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257).