A Novel Address Mapping Scheduling Strategy for Continuous Flow Parallel FFT Implementation

The paper proposes a new continuous flow parallel Fast Fourier Transform (FFT)processor using a novel address mapping scheduling strategy and two costefficient non-conflict address mapping approaches. Four parallel butterfly computation units enhance the high throughput. The novel address mapping scheduling strategy uses only two memory units for a continuous flow parallel FFT implementation, which reduces the utilization of the memory resources. The two non-conflict address mapping approaches not only guarantee the parallel computation of four butterfly units which can be finished in one clock cycle, but also guarantee the execution of the address mapping scheduling strategy; especially these non-conflict address mapping approaches are theoretically proved in the paper. The number of clock cycles is 320 for a 1024-point FFT; when it runs at 100MHz, the time is 3.2μs; when real and imaginary numbers are both 16bit, the required memory resources is only 8kbytes.Therefore the proposed parallel FFT processor can reduce the consumption of the memory resources and computation cycles compared with other FFT processors.