Suppression of endurance-stressed data-retention failures of 40nm TaOx-based ReRAM

This work investigates data-retention characteristics after different Set/Reset endurance cycles and voltages in 40nm TaOx based resistive random access memory (ReRAM). The reliability of ReRAM cells depends on data-retention time in low resistance state (LRS), while data-retention time of high resistance state (HRS) improves by the proposed novel write method “Finalize”. The current distribution of LRS shifts overall to the HRS side as data-retention time increases. Thus, the data-retention characteristics in LRS are determined by typical cells of the major current distribution. These phenomena are different from those of NAND flash memories where tail cells determine the data-retention time. A consistent physical model of both endurance-stress and retention-stress is proposed.